High Performance, Digital Output Gyroscope Data Sheet ADXRS453 FEATURES GENERAL DESCRIPTION Complete rate gyroscope on a single chip The ADXRS453 is an angular rate sensor (gyroscope) intended 300/sec angular rate sensing for industrial, instrumentation, and stabilization applications in Ultrahigh vibration rejection: 0.01/sec/g high vibration environments. An advanced, differential, quad Excellent 16/hour null bias stability sensor design rejects the influence of linear acceleration, enabling Internal temperature compensation the ADXRS453 to offer high accuracy rate sensing in harsh 2000 g powered shock survivability environments where shock and vibration are present. SPI digital output with 16-bit data-word The ADXRS453 uses an internal, continuous self-test architec- Low noise and low power ture. The integrity of the electromechanical system is checked by 3.3 V to 5 V operation applying a high frequency electrostatic force to the sense structure 40C to +105C operation to generate a rate signal that can be differentiated from the base- Ultrasmall, light, and RoHS compliant band rate data and internally analyzed. Two package options The ADXRS453 is capable of sensing an angular rate of up to Low cost SOIC CAV package for yaw rate (z-axis) response 300/sec. Angular rate data is presented as a 16-bit word that Innovative ceramic vertical mount package (LCC V) for is part of a 32-bit SPI message. pitch and roll response The ADXRS453 is available in a 16-lead plastic cavity SOIC APPLICATIONS (SOIC CAV) and an SMT-compatible vertical mount package Rotation sensing in high vibration environments (LCC V), and is capable of operating across a wide voltage Rotation sensing for industrial and instrumentation range (3.3 V to 5 V). applications High performance platform stabilization FUNCTIONAL BLOCK DIAGRAM V CP5 X HIGH VOLTAGE P GENERATION DD ADXRS453 LDO REGULATOR DV DD HV DRIVE AV DD CLOCK ARITHMETIC PHASE- DIVIDER LOGIC UNIT LOCKED LOOP DECIMATION AMPLITUDE FILTER DETECT MOSI TEMPERATURE BAND-PASS 12-BIT CALIBRATION MISO DEMOD SPI FILTER ADC INTERFACE SCLK CS FAULT Q FILTER Q DAQ DETECTION Z-AXIS ANGULAR RATE SENSOR DV SS SELF-TEST P DAQ CONTROL P SS AV SS EEPROM Figure 1. Rev. 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REGISTERS/MEMORY 09155-001ADXRS453 Data Sheet TABLE OF CONTENTS ADXRS453 Signal Chain Timing ............................................. 13 Features .............................................................................................. 1 SPI Communication Protocol ....................................................... 14 Applications ....................................................................................... 1 Command/Response ................................................................. 14 General Description ......................................................................... 1 Device Data Latching ................................................................. 15 Functional Block Diagram .............................................................. 1 SPI Timing Characteristics ....................................................... 16 Revision History ............................................................................... 2 Command/Response Bit Definitions ....................................... 17 Specif icat ions ..................................................................................... 3 Fault Register Bit Definitions ................................................... 18 Absolute Maximum Ratings ............................................................ 4 Recommended Start-Up Sequence with CHK Bit Thermal Resistance ...................................................................... 4 Asser tion ...................................................................................... 20 Rate Sensitive Axis ....................................................................... 4 Rate Data Format ............................................................................ 21 ESD Caution .................................................................................. 4 Memory Map and Registers .......................................................... 22 Pin Configurations and Function Descriptions ........................... 5 Memory Map .............................................................................. 22 Typical Performance Characteristics ............................................. 7 Memory Register Definitions ................................................... 23 Theory of Operation ........................................................................ 9 Package Orientation and Layout Information ............................ 25 Continuous Self-Test .................................................................... 9 Solder Profile............................................................................... 26 Mechanical Performance ............................................................... 10 Package Marking Codes ............................................................ 27 Noise Performance ......................................................................... 11 Outline Dimensions ....................................................................... 28 Applications Information .............................................................. 12 Ordering Guide .......................................................................... 29 Calibrated Performance ............................................................. 12 Mechanical Considerations for Mounting .............................. 12 Application Circuits ................................................................... 12 REVISION HISTORY 12/11Rev. A to Rev. B Changes to Features Section............................................................ 1 Changes to Rate Sensitive Axis Section ......................................... 4 Deleted Endnote 1, Table 3 .............................................................. 4 Deleted Figure 5 Renumbered Sequentially ................................. 6 Changes to Figure 4 .......................................................................... 6 Changes to Figure 32 ...................................................................... 25 Deleted Figure 36 ............................................................................ 26 6/11Rev. 0 to Rev. A Changes to Bit 30 and Bit 31 in Table 9 ....................................... 14 Updated Outline Dimensions ....................................................... 29 Changes to Ordering Guide .......................................................... 30 1/11Revision 0: Initial Version Rev. B Page 2 of 32