+5 Volt, Parallel Input a Complete 12-Bit DAC DAC8562 FEATURES FUNCTIONAL BLOCK DIAGRAM Complete 12-Bit DAC V No External Components DD REFOUT Single +5 Volt Operation DAC-8562 1 mV/Bit with 4.095 V Full Scale True Voltage Output, 65 mA Drive 12-BIT REF V DAC OUT Very Low Power 3 mW 12 APPLICATIONS AGND Digitally Controlled Calibration DAC REGISTER Servo Controls 12 Process Control Equipment PC Peripherals DGND CE DATA CLR GENERAL DESCRIPTION The DAC8562 is available in two different 20-pin packages, The DAC8562 is a complete, parallel input, 12-bit, voltage out- plastic DIP and SOL-20. Each part is fully specified for opera- put DAC designed to operate from a single +5 volt supply. Built tion over 40C to +85C, and the full +5 V 5% power supply using a CBCMOS process, these monolithic DACs offer the range. user low cost, and ease-of-use in +5 volt only systems. For MIL-STD-883 applications, contact your local ADI sales Included on the chip, in addition to the DAC, is a rail-to-rail office for the DAC8562/883 data sheet which specifies opera- amplifier, latch and reference. The reference (REFOUT) is tion over the 55C to +125C temperature range. trimmed to 2.5 volts, and the on-chip amplifier gains up the DAC output to 4.095 volts full scale. The user needs only sup- 1 ply a +5 volt supply. V = +5V DD 0.75 T = 55C, +25C, +125C A The DAC8562 is coded straight binary. The op amp output 0.5 swings from 0 to +4.095 volts for a one millivolt per bit resolu- 55C tion, and is capable of driving 5 mA. Built using low tempera- 0.25 ture-coefficient silicon-chrome thin-film resistors, excellent linearity error over temperature has been achieved as shown be- 0 low in the linearity error versus digital input code plot. 0.25 Digital interface is parallel and high speed to interface to the 0.5 fastest processors without wait states. The interface is very sim- +25C & +125C ple requiring only a single CE signal. An asynchronous CLR in- 0.75 put sets the output to zero scale. 1 0 1024 2048 3072 4096 DIGITAL INPUT CODE Decimal Figure 1. Linearity Error vs. Digital Input Code Plot REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703 LINEARITY ERROR LSBDAC8562SPECIFICATIONS ELECTRICAL CHARACTERISTICS ( V = +5.0 6 5%, R = No Load, 408C T +858C, unless otherwise noted) DD S A Parameter Symbol Condition Min Typ Max Units STATIC PERFORMANCE Resolution N Note 2 12 Bits Relative Accuracy INL E Grade 1/2 1/4 +1/2 LSB F Grade 1 3/4 +1 LSB Differential Nonlinearity DNL No Missing Codes 1 3/4 +1 LSB Zero-Scale Error V Data = 000 +1/2 +3 LSB ZSE H 3 Full-Scale Voltage V Data - FFF FS H E Grade 4.087 4.095 4.103 V F Grade 4.079 4.095 4.111 V Full-Scale Tempco TCV Notes 3, 4 16 ppm/C FS ANALOG OUTPUT Output Current I Data = 800 5 7mA OUT H Load Regulation at Half Scale LD R = 402 to , Data = 800 1 3 LSB REG L H 4 Capacitive Load C No Oscillation 500 pF L REFERENCE OUTPUT Output Voltage V 2.484 2.500 2.516 V REF Output Source Current I Note 5 5 7 mA REF Line Rejection LN 0.08 %/V REJ Load Regulation LD I = 0 to 5 mA 0.1 %/mA REG REF LOGIC INPUTS Logic Input Low Voltage V 0.8 V IL Logic Input High Voltage V 2.4 V IH Input Leakage Current I 10 A IL Input Capacitance C Note 4 10 pF IL 1, 4 INTERFACE TIMING SPECIFICATIONS Chip Enable Pulse Width t 30 ns CEW Data Setup t 30 ns DS Data Hold t 10 ns DH Clear Pulse Width t 20 ns CLRW 4 AC CHARACTERISTICS 6 Voltage Output Settling Time t To 1 LSB of Final Value 16 s S Digital Feedthrough 35 nV sec SUPPLY CHARACTERISTICS Positive Supply Current I V = 2.4 V, V = 0.8 V 3 6 mA DD IH IL V = 0 V, V = +5 V 0.6 1 mA IL DD Power Dissipation P V = 2.4 V, V = 0.8 V 15 30 mW DISS IH IL V = 0 V, V = +5V 3 5 mW IL DD Power Supply Sensitivity PSS V = 5% 0.002 0.004 %/% DD NOTES 1 All input control signals are specified with t = t = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V. r f 2 1 LSB = 1 mV for 0 to +4.095 V output range. 3 Includes internal voltage reference error. 4 These parameters are guaranteed by design and not subject to production testing. 5 Very little sink current is available at the REFOUT pin. Use external buffer if setting up a virtual ground. 6 The settling time specification does not apply for negative going transitions within the last 6 LSBs of ground. Some devices exhibit double the typical settling time in this 6 LSB region. Specifications subject to change without notice. 2 REV. A