DEMO CIRCUIT 1600 DC1600 QUICK START GUIDE FOR LTC6412+LTC2261 QUICK START GUIDE LTC6412 and LTC2261-14 Low-Power, Direct-to-Digital IF Receiver with Variable Gain DESCRIPTION The demonstration circuit 1600A supports the LTC6412 DC1600A supports the LTC2261 family s double-data Analog-Controlled VGA driving LTC s family of 1.8V, rate (DDR) low-voltage differential signaling (LVDS) data 14/12 Bit, 80-125Msps ADC s. The 1600A derives from output mode to the parallel data edge connector. This demonstration circuits 1369A and 1464A by combining DDR LVDS output mode and edge connector is fully the VGA and ADC functions with a suitable matching and compatible with the LTC DC890 FastDAACs interface anti-aliasing interface circuit to form a fully functional board and PScope data acquisition and analysis tools. direct-to-digital IF receiver. Figure 1 shows a simplified Connection to these evaluation tools is further described schematic of DC1600A. The nominal WCDMA perform- in this guide. ance of this VGA+ADC combination is described and re- ported in LTC Design Note DN482. Full circuit schemat- Design files for this circuit board are available. Call ics are included at the end of this document. the LTC factory. L, LTC, LTM, and LT are trademarks of Linear Technology Corporation. Other product names may be trademarks of the companies that manufacture the product. Figure 1. DC1600A Simplified Schematic 1 DC1600 QUICK START GUIDE FOR LTC6412+LTC2261 DEFAULT CONFIGURATION Demonstration circuit 1600A is currently available in one The encode clock is also configured for single-ended default assembly configuration featuring the LTC6412 drive to a high impedance digital input. This clock signal VGA and LTC2261-14 ADC with an interface circuit tuned requires proper filtering and termination to achieve the for a wideband IF at 140MHz. best ADC performance. These requirements are de- scribed further in this guide. The default assembly includes the LTC2261-14, but the user can substitute and assemble any of the 14/12 Bit The interface circuit layout between the VGA and ADC is ADC s from the LTC2261 family of products including flexible to accommodate a variety of tuning and matching LTC2261-14, LTC2261-12, LTC2260-14, LTC2260-12, circuits over an intermediate frequency range of 70MHz LTC2259-14, and LTC2259-12. to 240MHz. Several tuning options and component val- ues are described further in this guide. The input circuit to the VGA employs a balun to provide a single-ended 50 Ohm analog input impedance over a frequency range of 10MHz to 500MHz. Connections to the input balun can be reconfigured for 50 Ohm differen- tial drive. Table 1. Performance Summary (T = 25C) A PARAMETER CONDITION VALUE Depending on sampling rate and the ADC assembled, Optimized for 4.0V Supply Voltage DC1600A this supply must provide up to 250mA. 4.0V 6.0V min/max Set by SENSE pin voltage from EXT REF turret. With no connection to EXT REF, the SENSE pin voltage pulls ADC Analog Input Range 1V to 2V PP PP high to set the ADC analog input range to 2Vpp. Minimum Logic High 1.3V Logic Input Voltages Maximum Logic Low 0.6V Nominal Logic levels (100 load, 3.5mA Mode) 350mV/1.25V common mode Logic Output Voltages (differential) Minimum Logic levels (100 load, 3.5mA Mode) 247mV/1.25V common mode LTC2261 125 Msps Sampling Frequency (Convert Clock LTC2260 105 Msps Frequency) LTC2259 80 Msps Convert Clock Level Single ended Encode Mode (ENC- tied to GND) 03.6V Convert Clock Level Differential Encode Mode (ENC- not tied to GND) 0.2V3.6V LTC2261-14, LTC2260-14, LTC2259-14 14 Bits Resolution LTC2261-12, LTC2260-12, LTC2259-12 12 Bits Default Assembly Configuration 100MHz 180MHz Input frequency range With Modified VGA/ADC Interface Tuning 10MHz 270MHz ADC SFDR See Applicable Data Sheet for ADC specifications ADC SNR See Applicable Data Sheet for ADC specifications 2