Low Power HART Modem Data Sheet AD5700/AD5700-1 FEATURES GENERAL DESCRIPTION HART-compliant fully integrated FSK modem The AD5700/AD5700-1 are single-chip solutions, designed 1200 Hz and 2200 Hz sinusoidal shift frequencies and specified to operate as a HART FSK half-duplex modem, 115 A maximum supply current in receive mode complying with the HART physical layer requirements. The Suitable for intrinsically safe applications AD5700/AD5700-1 integrate all of the necessary filtering, signal Integrated receive band-pass filter detection, modulating, demodulating and signal generation Minimal external components required functions, thus requiring few external components. The 0.5% Clocking optimized for various system configurations precision internal oscillator on the AD5700-1 greatly reduces Ultralow power crystal oscillator (60 A maximum) the board space requirements, making it ideal for line-powered External CMOS clock source applications in both master and slave configurations. The maxi- Precision internal oscillator (AD5700-1only) mum supply current consumption is 115 A, making the AD5700/ Buffered HART outputextra drive capability AD5700-1 an optimal choice for low power loop-powered applica- 8 kV HBM ESD rating tions. Transmit waveforms are phase continuous 1200 Hz and 1.71 V to 5.5 V power supply 2200 Hz sinusoids. The AD5700/AD5700-1 contain accurate 1.71 V to 5.5 V interface carrier detect circuitry and use a standard UART interface. 40C to +125C operation Table 1. Related Products 4 mm 4 mm LFCSP package Part No. Description HART physical layer compliant AD5755-1 Quad-channel, 16-bit, serial input, 4 mA to 20 mA and UART interface voltage output DAC, dynamic power control, HART connectivity APPLICATIONS AD5421 16-bit, serial input, loop powered, 4 mA to 20 mA DAC Field transmitters AD5410/ Single-channel, 12-bit/16-bit, serial input, 4 mA to 20 mA HART multiplexers AD5420 current source DACs PLC and DCS analog I/O modules AD5412/ Single-channel, 12-bit/16-bit, serial input, current HART network connectivity AD5422 source and voltage output DACs FUNCTIONAL BLOCK DIAGRAM V REG CAP CLKOUT XTAL1 XTAL2 XTAL EN CC IOV CC OSC AD5700/AD5700-1 DUPLEX BUFFER CD FSK DAC HART OUT MODULATOR RXD ADC IP TXD BAND-PASS FSK ADC FILTER AND HART IN DEMODULATOR RTS BIASING CLK CFG0 VOLTAGE REFERENCE CLK CFG1 RESET DGND REF REF EN AGND FILTER SEL Figure 1. Rev. G Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 78 1.32 9.47 00 20122016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technica l Support www.analog.com CONTROL LOGIC 10435-001AD5700/AD5700-1 Data Sheet TABLE OF CONTENTS Features .....................................................................................1 FSK Modulator .................................................................... 13 Applications...............................................................................1 Connecting to HART OUT ................................................ 14 General Description ..................................................................1 FSK Demodulator................................................................ 14 Functional Block Diagram.........................................................1 Connecting to HART IN or ADC IP ................................. 14 Revision History ........................................................................2 Clock Configuration ............................................................ 15 Specifications .............................................................................3 Supply Current Calculations................................................ 16 Timing Characteristics...........................................................5 Power-Down Mode ............................................................. 16 Absolute Maximum Ratings ......................................................6 Full Duplex Operation......................................................... 16 Thermal Resistance ................................................................6 Applications Information ........................................................ 17 ESD Caution ..........................................................................6 Supply Decoupling............................................................... 17 Pin Configuration and Function Descriptions...........................7 Transient Voltage Protection................................................ 17 Typical Performance Characteristics .........................................9 Typical Connection Diagrams ............................................. 18 Terminology ............................................................................12 Outline Dimensions ................................................................ 21 Theory of Operation................................................................13 Ordering Guide ................................................................... 21 REVISION HISTORY 12/2016Rev. F to Rev. G 7/2012Rev. A to Rev. B Changes to Figure 2 and Table 6 ................................................7 Removed V and IOV Current Consumption Text, Table 2.. 3 CC CC Added Internal Oscillator and External Clock Parameters 1/2014Rev. E to Rev. F to Table 2 ................................................................................... 4 Changes to Figure 3 to Figure 7 .................................................9 Changes to t Description and Endnote 2, Table 3..................... 5 2 Changes to Example Section....................................................14 Changes to IOV Description, Table 6 ..................................... 7 CC Added Supply Current Calculations Section ........................... 16 10/2013Rev. D to Rev. E Added Transient Voltage Protection Section, Figure 26, and Changes to t and t Descriptions, Table 3..................................5 Figure 27 Renumbered Sequentially ....................................... 17 7 8 Changed JA from 30C/W to 56C/W .......................................6 Changes to Typical Connection Diagrams Section.................. 18 Added Figure 13 and Figure 14................................................10 Changes to Figure 29 ............................................................... 19 Changes to External Crystal Section and Figure 25 .................15 Changes to Figure 30 ............................................................... 20 Updated Outline Dimensions.................................................. 21 5/2013Rev. C to Rev. D 4/2012Rev. 0 to Rev. A 2/2013Rev. B to Rev. C Change to Transmit Impedance Parameter, Low, Table 2 .. 4 RTS Changed 2 V to 5.5 V Power Supply to 1.71 V to 5.5 V Power Changes to Figure 3, Figure 4, Figure 5, and Figure 7................ 9 Supply, Features Section ............................................................1 Changes to Figure 10 and Figure 11 ........................................ 10 Changes to Summary Statement, V Parameter, and Internal CC Changed AD5755 to AD5755-1 Throughout .......................... 17 Reference Voltage Parameter Test Conditions/Comments, Change to Figure 27 ................................................................ 18 Table 2 .......................................................................................3 Changed V = 2 V to 5.5 V to V = 1.71 V to 5.5 V in the CC CC 2/2012Revision 0: Initial Version Summary Statement, Table 3 .....................................................5 Changes to Pin 18 Description and EPAD Mnemonic and Description, Table 6 ...................................................................7 Changes to Figure 9 and Figure 13 ..........................................10 Changes to Figure 28 ...............................................................18 Change to Figure 30.................................................................20 Rev. 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