19-6312 Rev 6/12 DS1321 Flexible Nonvolatile Controller with Lithium Battery Monitor FEATURES PIN ASSIGNMENT Converts CMOS SRAM into nonvolatile V 1 16 V CCO CCI memory V 2 15 RST BAT Unconditionally write-protects SRAM when TOL 3 14 BW V is out of tolerance CC CEI1 4 13 CEO1 Automatically switches to battery backup CEI2 5 12 CEO2 supply when V power failure occurs CC A/CEI3 6 11 CEO3 Flexible memory organization B/CEI4 7 10 CEO4 GND 8 9 MODE - Mode 0: 4 banks with 1 SRAM each - Mode 1: 2 banks with 2 SRAMs each DS1321 16-Pin PDIP (300 mils) - Mode 2: 1 bank with 4 SRAMs each Monitors voltage of a lithium cell and provides advanced warning of impending battery failure V 1 16 V CCO CCI Signals low-battery condition on active low V 2 15 RST BAT Battery Warning output signal TOL 3 14 BW Resets processor when power failure occurs CEI1 4 13 CEO1 CEI2 5 12 CEO2 and holds processor in reset during system A/CEI3 6 11 CEO3 power-up B/CEI4 7 10 CEO4 Optional 5% or 10% power-fail detection GND 8 9 MODE 16-pin PDIP, 16-pin SO and 20-pin TSSOP DS1321S 16-Pin SO packages (150 mils) Industrial temperature range of -40C to +85C PIN DESCRIPTION V 1 20 V CCO CCI V 2 19 RST BAT V - +5V Power Supply Input CCI TOL 3 18 BW V - SRAM Power Supply Output CCO 17 CEI1 4 CEO1 V - Backup Battery Input BAT CEI2 5 16 CEO2 A, B - Address Inputs NC 6 NC 15 CEI1 - CEI4 - Chip Enable Inputs A/CEI3 7 14 CEO3 B/CEI4 8 13 CEO4 CEO1 - CEO4 - Chip Enable Outputs NC 9 12 NC TOL - V Tolerance Select CC GND 10 11 MODE BW - Battery Warning Output (Open DS1321E 20-Pin TSSOP Drain) - Reset Output (Open Drain) RST MODE - Mode Input GND - Ground NC - No Connection 1 of 13 DS1321 DESCRIPTION The DS1321 Flexible Nonvolatile Controller with Lithium Battery Monitor is a CMOS circuit which solves the application problem of converting CMOS SRAMs into nonvolatile memory. Incoming power is monitored for an out-of-tolerance condition. When such a condition is detected, chip enable outputs are inhibited to accomplish write protection and the battery is switched on to supply the SRAMs with uninterrupted power. Special circuitry uses a low-leakage CMOS process which affords precise voltage detection at extremely low battery consumption. One DS1321 can support as many as four SRAMs arranged in any of three memory configurations. In addition to battery-backup support, the DS1321 performs the important function of monitoring the remaining capacity of the lithium battery and providing a warning before the battery reaches end-of-life. Because the open-circuit voltage of a lithium backup battery remains relatively constant over the majority of its life, accurate battery monitoring requires loaded-battery voltage measurement. The DS1321 performs such measurement by periodically comparing the voltage of the battery as it supports an internal resistive load with a carefully selected reference voltage. If the battery voltage falls below the reference voltage under such conditions, the battery will soon reach end-of-life. As a result, the Battery Warning pin is activated to signal the need for battery replacement. MEMORY BACKUP The DS1321 performs all the circuit functions required to provide battery-backup for as many as four SRAMs. First, the device provides a switch to direct power from the battery or the system power supply (V ). Whenever V is less than the V trip point and V is less than the battery voltage V , the CCI CCI CCTP CCI BAT battery is switched in to provide backup power to the SRAM. This switch has voltage drop of less than 0.2 volts. Second, the DS1321 handles power failure detection and SRAM write-protection. V is constantly CCI monitored, and when the supply goes out of tolerance, a precision comparator detects power failure and inhibits the four chip enable outputs in order to write-protect the SRAMs. This is accomplished by holding through to within 0.2 volts of V when V is out of tolerance. If any is CEO1 CEO4 CEI CCO CCI active (low) at the time that power failure is detected, the corresponding signal is kept low until the CEO signal is brought high again. Once the signal is brought high, the signal is taken high and CEI CEI CEO held high until after V has returned to its nominal voltage level. If the signal is not brought high CEI CCI by 1.5 s after power failure is detected, the corresponding is forced high at that time. This specific CEO scheme for delaying write protection for up to 1.5 s guarantees that any memory access in progress when power failure occurs will complete properly. Power failure detection occurs in the range of 4.75 to 4.5 volts (5% tolerance) when the TOL pin is wired to GND or in the range of 4.5 to 4.25 volts (10% tolerance) when TOL is connected to V . CCO 2 of 13