X-On Electronics has gained recognition as a prominent supplier of EVAL-AD5750EBZ Amplifier IC Development Tools across the USA, India, Europe, Australia, and various other global locations. EVAL-AD5750EBZ Amplifier IC Development Tools are a product manufactured by Analog Devices. We provide cost-effective solutions for Amplifier IC Development Tools, ensuring timely deliveries around the world.

EVAL-AD5750EBZ Analog Devices

EVAL-AD5750EBZ electronic component of Analog Devices
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Part No.EVAL-AD5750EBZ
Manufacturer: Analog Devices
Category: Amplifier IC Development Tools
Description: Analog Devices Amplifier IC Development Tools EVAL BRD AD5750
Datasheet: EVAL-AD5750EBZ Datasheet (PDF)
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



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1: USD 162.1725 ea
Line Total: USD 162.17 
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MOQ: 1  Multiples: 1
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Industrial Current/Voltage Output Driver with Programmable Ranges Data Sheet AD5750/AD5750-1/AD5750-2 The output current range is programmable across five current FEATURES ranges: 4 mA to 20 mA, 0 mA to 20 mA, 0 mA to 24 mA, 20 mA, Current output ranges: 4 mA to 20 mA, 0 mA to 20 mA, 0 mA and 24 mA. An overrange of 2% is available on the unipolar to 24 mA, 20 mA, and 24 mA current ranges. 0.03% full-scale range (FSR) total unadjusted error (TUE) 5 ppm/C typical output drift Voltage output is provided from a separate pin that can be Voltage output ranges: 0 V to 5 V, 0 V to 10 V, 5 V, and 10 V configured to provide 0 V to 5 V, 0 V to 10 V, 5 V, or 10 V with 20% overrange output ranges. An overrange of 20% is available on the voltage 0.02% FSR TUE ranges. 3 ppm/C typical output drift Analog outputs are short-circuit and open-circuit protected and Flexible serial digital interface can drive capacitive loads of 1 F and inductive loads of 0.1 H. On-chip output fault detection The devices are specified to operate with a power supply range Packet error checking (PEC) from 12 V to 24 V. Output loop compliance is 0 V to AV DD Asynchronous CLEAR function 2.75 V. Flexible power-up condition to 0 V or tristate Power supply range The flexible serial interface is SPI and MICROWIRE compatible AV : +12 V ( 10%) to +24 V ( 10%) DD and can operate in 3-wire mode to minimize the digital isolation AV : 12 V ( 10%) to 24 V ( 10%) SS required in isolated applications. The interface also features an Output loop compliance to AV 2.75 V DD optional PEC feature using CRC-8 error checking, useful in Temperature range: 40C to +105C industrial environments where data communication corruption 32-lead, 5 mm 5 mm LFCSP package can occur. The devices also include a power-on-reset function, ensuring that APPLICATIONS the devices power up in a known state (0 V or tristate), and an Process controls asynchronous CLEAR pin that sets the outputs to a zero scale/mid- Actuator controls scale voltage output or the low end of the selected current range. PLCs The HW SELECT pin is used to configure the parts for hardware GENERAL DESCRIPTION or software mode on power-up. The AD5750/AD5750-1/AD5750-2 are single-channel, low cost, Table 1. Related Devices precision voltage/current output drivers with hardware- or software-programmable output ranges. The software ranges are Part Number Description configured via an SPI-/MICROWIRE-compatible serial interface. AD5422 Single channel, 16-bit, serial input current source and voltage output DAC The AD5750/AD5750-1/AD5750-2 target applications in PLC AD5751 Industrial I/V output driver, single supply, 55 V and industrial process control. The analog input to the AD5750/ maximum supply, programmable ranges AD5750-1/AD5750-2 is provided from a low voltage, single-supply AD5420 Single channel, 16-bit, serial input, 4 mA to digital-to-analog converter (DAC) and is internally conditioned 20 mA current source DAC to provide the desired output current/voltage range. Analog input ranges available are 0 V to 2.5 V (AD5750-1/AD5750-2) or 0 V to 4.096 V (AD5750). Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20092014 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. AD5750/AD5750-1/AD5750-2 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 OUTE N ........................................................................................ 26 Applications ....................................................................................... 1 Software Control ........................................................................ 26 General Description ......................................................................... 1 Hardware Control ...................................................................... 28 Revision History ............................................................................... 2 Transfer Function ....................................................................... 28 Functional Block Diagram .............................................................. 3 Detailed Description of Features .................................................. 29 Specif icat ions ..................................................................................... 4 Output Fault AlertSoftware Mode ....................................... 29 Timing Characteristics ................................................................ 8 Output Fault AlertHardware Mode ..................................... 29 Absolute Maximum Ratings .......................................................... 10 Voltage Output Short-Circuit Protection ................................ 29 ESD Caution ................................................................................ 10 Asynchronous Clear (CLEAR) ................................................. 29 Pin Configuration and Function Descriptions ........................... 11 External Current Setting Resistor ............................................ 30 Typical Performance Characteristics ........................................... 13 Programmable Overrange Modes ............................................ 30 Voltage Output ............................................................................ 13 Packet Error Checking ............................................................... 30 Current Output ........................................................................... 17 Applications Information .............................................................. 31 Terminology .................................................................................... 22 Transient Voltage Protection .................................................... 31 Theory of Operation ...................................................................... 23 Thermal Considerations ............................................................ 31 Software Mode ............................................................................ 23 Layout Guidelines....................................................................... 31 Current Output Architecture .................................................... 25 Galvanically Isolated Interface ................................................. 32 Driving Inductive Loads ............................................................ 25 Microprocessor Interfacing ....................................................... 32 Power-On State of AD5750/AD5750-1/AD5750-2 ................... 25 Outline Dimensions ....................................................................... 33 Default Registers at Power-On ................................................. 26 Ordering Guide .......................................................................... 33 Reset Function ............................................................................ 26 REVISION HISTORY 9/14Rev. E to Rev. F 7/10Rev. B to Rev. C Changes to Accuracy, Internal R Parameter, Table 2 ............... 6 Added Leakage Current in Voltage Output Characteristics SET Changes to Table 4 .......................................................................... 10 Parameter (Table 2) ........................................................................... 5 Changes to Figure 4 ........................................................................ 11 Added Leakage Current in Current Output Characteristics Changes to Figure 46 ...................................................................... 20 Parameter (Table 2) ........................................................................... 6 Changes to Asynchronous Clear (CLEAR) Section ................... 29 6/10Rev. A to Rev. B Changes to Thermal Consideration Section ............................... 31 Changes to Table 1 ............................................................................. 1 Updated Outline Dimensions ....................................................... 33 Changes to Table 2, Power Requirements ...................................... 7 Changes to Ordering Guide .......................................................... 33 8/09Rev. 0 to Rev. A 6/12Rev. D to Rev. E Added AD5750-1................................................................ Universal Changes to Figure 3 .......................................................................... 9 Changes to Features and General Description Sections .............. 1 Changes to Status Bit Read Operation Section ........................... 28 Changes to Table 2 ............................................................................. 4 Updated Outline Dimensions ....................................................... 33 Changes to Theory of Operation Section and Figure 51 .......... 23 4/12Rev. C to Rev. D Change to Figure 52 and Table 6 Title ......................................... 24 Added AD5750-2 ................................................................ Universal Changes to Current Output Architecture Section and Power-On Changes to Table 2 ............................................................................ 4 State of AD5750/AD5750-1 .......................................................... 25 Updated Outline Dimensions ....................................................... 33 Changes to Transfer Function Section ........................................ 28 Changes to Ordering Guide .......................................................... 33 Changes to Programmable Overrange Modes Section ............. 30 Changes to Ordering Guide .......................................................... 33 7/09Revision 0: Initial Version Rev. F Page 2 of 36

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