Dual, High Speed ECL Comparators Data Sheet ADCMP563/ADCMP564 FEATURES FUNCTIONAL BLOCK DIAGRAMS HYS* Differential ECL-compatible outputs 700 ps propagation delay input to output NONINVERTING Q OUTPUT 75 ps propagation delay dispersion INPUT ADCMP563/ Input common-mode range: 2.0 V to +3.0 V ADCMP564 Robust input protection INVERTING Q OUTPUT INPUT Differential latch control Internal latch pull-up resistors LATCH ENABLE Power supply rejection greater than 85 dB LATCH ENABLE INPUT INPUT 700 ps minimum pulse width *ADCMP564 ONLY 1.5 GHz equivalent input rise time bandwidth Figure 1. Typical output rise/fall time of 500 ps ESD protection > 4kV HBM, >200V MM 1 16 QB QA Programmable hysteresis 2 15 QB QA 3 14 GND APPLICATIONS GND ADCMP563 LEA 4 13 LEB Automatic test equipment BRQ 5 12 LEA TOP VIEW LEB High speed instrumentation (Not to Scale) 6 11 V V Scope and logic analyzer front ends CC EE 7 10 INB Window comparators INA +INA 8 9 +INB High speed line receivers Threshold detection Peak detection Figure 2. ADCMP563 16-Lead QSOP High speed triggers GND 1 20 GND Patient diagnostics QA 2 19 QB Hand-held test instruments QA QB 3 18 Zero crossing detectors ADCMP564 GND 4 17 GND Line receivers and signal restoration BRQ LEA 5 16 LEB Clock drivers TOP VIEW (Not to Scale) LEA 6 15 LEB GENERAL DESCRIPTION V 7 14 V EE CC The ADCMP563/ADCMP564 are high speed comparators INA INB 8 13 fabricated on Analog Devices proprietary XFCB process. The +INA +INB 9 12 devices feature a 700 ps propagation delay with less than 75 ps HYSA 10 11 HYSB overdrive dispersion. Dispersion, a measure of the difference in Figure 3. ADCMP564 20-Lead QSOP propagation delay under differing overdrive conditions, is a partic- ularly important characteristic of high speed comparators. A separate programmable hysteresis pin is available on the ADCMP564. INA 1 12 QA A differential input stage permits consistent propagation delay +INA 2 11 QA with a wide variety of signals in the common-mode range from ADCMP563 BCP 10 +INB 3 QB 2.0 V to +3.0 V. Outputs are complementary digital signals that TOP VIEW INB 4 9 QB (Not to Scale) are fully compatible with ECL 10 K and 10 KH logic families. The outputs provide sufficient drive current to directly drive transmission lines terminated in 50 to 2 V. A latch input, which is included, permits tracking, track-and-hold, or sample- NOTES and-hold modes of operation. The latch input pins contain internal 1. THE EXPOSED PAD SHOULD BE EITHER CONNECTED TO VEE OR LEFT FLOATING. pull-ups that set the latch in tracking mode when left open. Figure 4. ADCMP563 16-Lead LFCSP The ADCMP563/ADCMP564 are specified over the industrial temperature range (40C to +85C). Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20072016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com V V CC EE LEB LEA LEB LEA GND GND 04650-0-002 04650-0-012 04650-0-001 04650-0-026 5 16 6 15 14 7 8 13ADCMP563/ADCMP564 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Timing Information ....................................................................... 10 Applications ....................................................................................... 1 Application Information ................................................................ 11 General Description ......................................................................... 1 Clock Timing Recovery ............................................................. 11 Functional Block Diagrams ............................................................. 1 Optimizing High Speed Performance ..................................... 11 Specifications ..................................................................................... 3 Comparator Propagation Delay Dispersion ............................... 11 Absolute Maximum Ratings ............................................................ 5 Comparator Hysteresis .............................................................. 12 Thermal Considerations .............................................................. 5 Minimum Input Slew Rate Requirement ................................ 12 ESD Caution .................................................................................. 5 Typical Application Circuits ......................................................... 13 Pin Configurations and Function Descriptions ........................... 6 Outline Dimensions ....................................................................... 14 Typical Performance Characteristics ............................................. 8 Ordering Guide .......................................................................... 15 REVISION HISTORY Changes to Table 1 ............................................................................. 3 4/16Rev. C to Rev. D Changes to Optimizing High Speed Performance Section ....... 11 Changes to Figure 4 .......................................................................... 1 Changes to Comparator Hysteresis Section ................................ 12 Changes to Figure 7 .......................................................................... 6 Changes to Minimum Input Slew Rate Requirement Section . 12 Updates Outline Dimensions ........................................................ 15 Changes to Ordering Guide .......................................................... 14 Changes to Ordering Guide .......................................................... 15 7/04Rev. 0 to Rev. A 6/11Rev. B to Rev. C Changes to Specification Table ........................................................ 4 Changes to Figure 4 .......................................................................... 1 Changes to Figure 14 ......................................................................... 9 Changes to Figure 7 and LFCSP Pin Numbers (Table 3) ............ 6 Changes to Figure 21 ...................................................................... 12 Updated Outline Dimensions ....................................................... 14 Changes to Figure 23 ...................................................................... 13 Changes to Ordering Guide .......................................................... 15 4/04Revision 0: Initial Version 5/05Rev. A to Rev. B Added 16-Lead LFCSP ....................................................... Universal Changes to Applications .................................................................. 1 Rev. D Page 2 of 15