Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply TTL/CMOS Comparators ADCMP600/ADCMP601/ADCMP602 FEATURES FUNCTIONAL BLOCK DIAGRAM Fully specified rail to rail at V = 2.5 V to 5.5 V CC Input common-mode voltage from 0.2 V to V + 0.2 V NONINVERTING CC INPUT Low glitch CMOS-/TTL-compatible output stage ADCMP600/ ADCMP601/ Q OUTPUT 3.5 ns propagation delay ADCMP602 10 mW at 3.3 V INVERTING INPUT Shutdown pin Single-pin control for programmable hysteresis and latch Power supply rejection > 50 dB LE/HYS S DN (EXCEPT ADCMP600) (ADCMP602 ONLY) Improved replacement for MAX999 Figure 1. 40C to +125C operation APPLICATIONS High speed instrumentation Clock and data signal restoration Logic level shifting or translation Pulse spectroscopy High speed line receivers Threshold detection Peak and zero-crossing detectors High speed trigger circuitry Pulse-width modulators Current/voltage-controlled oscillators Automatic test equipment (ATE) GENERAL DESCRIPTION input signal range while still allowing independent output The ADCMP600, ADCMP601, and ADCMP602 are very fast swing control and power savings. comparators fabricated on XFCB2, an Analog Devices, Inc. proprietary process. These comparators are exceptionally The TTL-/CMOS-compatible output stage is designed to drive versatile and easy to use. Features include an input range from up to 5 pF with full timing specs and to degrade in a graceful GND 0.5 V to V + 0.2 V, low noise, TTL-/CMOS-compatible CC and linear fashion as additional capacitance is added. The output drivers, and latch inputs with adjustable hysteresis comparator input stage offers robust protection against large and/or shutdown inputs. input overdrive, and the outputs do not phase reverse when the valid input signal range is exceeded. Latch and programmable The device offers 5 ns propagation delay with 10 mV overdrive hysteresis features are also provided with a unique single-pin on 3 mA typical supply current. control option. A flexible power supply scheme allows the devices to operate The ADCMP600 is available in 5-lead SC70 and SOT-23 with a single +2.5 V positive supply and a 0.5 V to +2.8 V packages, the ADCMP601 is available in a 6-lead SC70 package, input signal range up to a +5.5 V positive supply with a 0.5 V and the ADCMP602 is available in an 8-lead MSOP package. to +5.8 V input signal range. Split input/output supplies with no sequencing restrictions on the ADCMP602 support a wide Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 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All rights reserved. 05914-001ADCMP600/ADCMP601/ADCMP602 TABLE OF CONTENTS Features .............................................................................................. 1 Application Information ................................................................ 10 Applications ....................................................................................... 1 Power/Ground Layout and Bypassing ..................................... 10 Functional Block Diagram .............................................................. 1 TTL-/CMOS-Compatible Output Stage ................................. 10 General Description ......................................................................... 1 Using/Disabling the Latch Feature ........................................... 10 Revision History ............................................................................... 2 Optimizing Performance ........................................................... 11 Specifications ..................................................................................... 3 Comparator Propagation Delay Dispersion ........................... 11 Electrical Characteristics ............................................................. 3 Comparator Hysteresis .............................................................. 11 Timing Information ......................................................................... 5 Crossover Bias Point .................................................................. 12 Absolute Maximum Ratings ............................................................ 6 Minimum Input Slew Rate Requirement ................................ 12 Thermal Resistance ...................................................................... 6 Typical Application Circuits ......................................................... 13 ESD Caution .................................................................................. 6 Outline Dimensions ....................................................................... 14 Pin Configuration and Function Descriptions ............................. 7 Ordering Guide .......................................................................... 16 Typical Performance Characteristics ............................................. 8 REVISION HISTORY 1/11Rev. 0 to Rev. A Changed V Pin to GND ............................................. Throughout EE Changes to Common-Mode Dispersion Conditions................... 4 Changes to Figure 15 and Figure 16 ............................................... 9 Changes to Comparator Hysteresis Section ................................ 12 Updated Outline Dimensions ....................................................... 14 Changes to Ordering Guide .......................................................... 15 10/06Revision 0: Initial Version Rev. A Page 2 of 16