Super Sequencer with Interchip Bus and Nonvolatile Fault Recording Data Sheet ADM1260 FEATURES FUNCTIONAL BLOCK DIAGRAM REFOUT REFGND REFIN CDA CCL SDA SCL A1 A0 Complete supervisory and sequencing solution for up to 10 supplies per device VREF INTERCHIP SMBus BUS Interchip bus (ICB) simplifies multidevice connections and INTERFACE ADM1260 sequencing system operation 12-BIT EEPROM Supports up to 4 devices SAR ADC 16 event deep black box nonvolatile fault recording FAULT CLOSED-LOOP RECORDING MARGINING SYSTEM 10 supply fault detectors enable supervision of supplies VX1 PDO1 CONFIGURABLE <0.5% accuracy at all voltages at 25C DUAL- OUTPUT PDO2 VX2 FUNCTION DRIVERS INPUTS <1.0% accuracy across all voltages and temperatures PDO3 VX3 (HV CAPABLE OF PDO4 (LOGIC INPUTS DRIVING GATES 5 selectable input attenuators allow supervision of supplies VX4 OR PDO5 OF N-FET) SFDs) VX5 PDO6 14.4 V on VH and 6.0 V on VP1 to VP4 (VPx) SEQUENCING ENGINE 5 dual function inputs: VX1 to VX5 (VXx) VP1 PDO7 CONFIGURABLE High impedance input to supply fault detector with PROGRAMMABLE OUTPUT VP2 RESET DRIVERS PDO8 GENERATORS thresholds between 0.573 V and 1.375 V VP3 (LV CAPABLE PDO9 (SFDs) OF DRIVING VP4 General-purpose logic input LOGIC SIGNALS) VH PDO10 10 programmable driver outputs: PDO1 to PDO10 (PDOx) AGND PDOGND Open-collector with an external pull-up resistor V V V V V V V DD OUT OUT OUT OUT OUT OUT VDDCAP ARBITRATOR DAC DAC DAC DAC DAC DAC Push/pull output, driven to VDDCAP or VPx Open-collector with weak pull-up to VDDCAP or VPx DAC1 DAC2 DAC3 DAC4 DAC5 DAC6 VCCP GND Internally charge pumped high drive for use with external Figure 1. N-FET (PDO1 to PDO6 only) Sequencing engine (SE) implements state machine control of APPLICATIONS the PDOx outputs Central office systems State changes conditional on input events Servers/routers Enables complex control of boards Multivoltage system line cards Power-up and power-down sequence control Digital signal processor (DSP)/field programmable gate Fault event handling array (FPGA) supply sequencing Interrupt generation on warnings In-circuit testing of margined supplies Watchdog function can be integrated in the SE Program software control of sequencing through the SMBus Complete voltage margining solution for 6 voltage rails 6 output voltage 8-bit DACs (0.300 V to 1.552 V) allow voltage adjustment via dc-to-dc converter trim/feedback node 12-bit ADC for readback of all supervised voltages Reference input (REFIN) with two input options Driven directly from the 2.048 V (0.25%) REFOUT pin External reference for improved ADC performance Powered by the highest voltage on either VPx or VH Voltage on VPx or VH must be greater than the undervoltage lockout (UVLO) threshold Electronically erasable programmable read-only memory (EEPROM) Industry-standard, 2-wire bus interface (SMBus) PDOx pins guaranteed low with VH and VPx = 1.2 V Available in a 40-lead, 6 mm 6 mm LFCSP package Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. MUX 12445-001ADM1260 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Writing to the DACs .................................................................. 27 Functional Block Diagram .............................................................. 1 Choosing the Size of the Attenuation Resistor ....................... 27 Applications ....................................................................................... 1 DAC Limiting and Other Safety Features ............................... 27 Revision History ............................................................................... 3 Applications Information .............................................................. 28 General Description ......................................................................... 4 Multiple Devices Linked by ICB and Power Island Management ............................................................................... 28 Detailed Functional Block Diagram .............................................. 4 Communicating with the ADM1260 ........................................... 30 Specif icat ions ..................................................................................... 5 Configuration Download at Power-Up ................................... 30 Absolute Maximum Ratings ............................................................ 9 Updating the Configuration ..................................................... 30 Thermal Resistance ...................................................................... 9 Updating the Sequencing Engine ............................................. 31 ESD Caution .................................................................................. 9 Internal Registers ........................................................................ 31 Pin Configuration and Function Descriptions ........................... 10 EEPROM ..................................................................................... 31 Typical Performance Characteristics ........................................... 11 Serial Bus Interface ..................................................................... 31 Test Circuits ..................................................................................... 14 SMBus Protocols for RAM and EEPROM .............................. 33 Powering the ADM1260 ................................................................ 15 Write Operations ........................................................................ 34 Slew Rate Considerations .......................................................... 15 Read Operations ......................................................................... 35 Inputs ................................................................................................ 16 Interchip Bus ................................................................................... 37 Supply Supervision ..................................................................... 16 Overview ..................................................................................... 37 Programming the Supply Fault Detectors ............................... 16 Message Formats ........................................................................ 37 Input Comparator Hysteresis .................................................... 16 ICB Addressing and Event ........................................................ 37 Input Glitch Filtering ................................................................. 17 ICB Fault Handling .................................................................... 38 Supply Supervision with the VXx Inputs ................................ 17 ICB Pull-Up Resistor ................................................................. 38 VXx Pins as Digital Inputs ........................................................ 18 Configuration Registers ................................................................. 39 Outputs ............................................................................................ 19 Updating the Memory, Enabling Block Erasure, and Supply Sequencing Through Configurable Output Drivers ...... 19 Downloading EEPROM ............................................................ 39 Default Output Configuration .................................................. 19 Inputs ........................................................................................... 40 Sequencing Engine ......................................................................... 20 Outputs ........................................................................................ 48 O ver vie w ...................................................................................... 20 Sequencing Engine ..................................................................... 54 Warnings ...................................................................................... 20 Configuring Sequence Engine States to Write into the Black SMBus Jump (Unconditional Jump) ........................................ 20 Box EEPROM ............................................................................. 58 Interchip Bus ............................................................................... 21 ADC ............................................................................................. 60 SE Application Example ............................................................ 21 DACs ............................................................................................ 63 Fault and Status Reporting ........................................................ 23 Warnings, Faults, and Status ..................................................... 66 Nonvolatile Black Box Fault Recording ................................... 24 Black Box Status Registers and Fault Records ........................ 67 Black Box Writes with No External Supply ............................. 24 Use of the REVID Register ........................................................ 69 Voltage Readback ............................................................................ 25 Interchip Bus Configuration ..................................................... 69 Supply Supervision with the ADC ........................................... 25 Register Map Quick Reference ..................................................... 70 Supply Margining ........................................................................... 26 Outline Dimensions ....................................................................... 71 O ver vie w ...................................................................................... 26 Ordering Guide .......................................................................... 71 Open-Loop Supply Margining ................................................. 26 Closed-Loop Supply Margining ............................................... 26 Rev. 0 Page 2 of 71