32 Gbps, Dual Channel, Advanced Linear Equalizer Data Sheet HMC6545 FEATURES FUNCTIONAL BLOCK DIAGRAM Supports data rates from dc up to 32 Gbps Protocol and data rate agnostic Low latency (<170 ps) Integrated AGC with differential sensitivity of <50 mV Up to 20 dB programmable multiple unit interval input equalization HMC6545 GND 1 GND 24 Extended chromatic and polarization mode dispersion T/2 T/2 T/2 T/2 INP0 OUTP0 2 23 AGC tolerance INN0 3 22 OUTN0 Programmable differential output amplitude control of up to LPF c0 c1 c2 cn GND 4 21 GND 600 mV GND 5 20 GND SERIAL CONTROL Single 3.3 V supply eliminating external regulators REGISTERS INP1 6 19 OUTP1 Wide temperature range from 40C to +95C AGC T/2 T/2 T/2 T/2 INN1 7 18 OUTN1 5 mm 5 mm, 32-lead LFCSP package d0 d1 d2 dn LPF 17 GND GND 8 APPLICATIONS 40 Gbps/100 Gbps DQPSK direct detection receivers PACKAGE BASE Short and long reach CFP2 and QSFP+ modules CEI-28G MR and CEI-25G LR 100 GE line cards GND 16 Gbps and 32 Gbps Fibre Channel Figure 1. Infiniband 14 Gbps FDR and 28 Gbps EDR rates Signal conditioning for backplane and line cards Broadband test and measurement equipment GENERAL DESCRIPTION The HMC6545 is a low power, high performance, fully input of the FFE. The 9-tap FFE is programmed via 2-wire programmable, dual-channel, asynchronous advanced linear interface to generate wide range frequency responses that are equalizer that operates at data rates of up to 32 Gbps. The precursor or postcursor in nature for compensating signal HMC6545 is protocol and data rate agnostic, and it can operate impairments. After FFE tap coefficients are summed at the on the transmit path to predistort a transmitted signal to invert summing node, the signal is received by a linear output driver. channel distortion or on the receiver path to equalize the DC offset correction circuitry is controlled either automatically distorted and attenuated received signal. The HMC6545 is or manually via Forward Error Correction (FEC). effective in dealing with chromatic and polarization mode All high speed differential inputs and outputs of the HMC6545 are dispersion and intersymbol interference (ISI) caused by a wide current mode logic (CML) and terminated on chip with 50 to variety of transmission media (backplane or fiber) and channel the positive supply, 3.3 V, and can be dc-coupled or ac-coupled. lengths. The inputs and outputs of the HMC6545 can be operated either The HMC6545 consists of an automatic gain control (AGC) differentially or single-ended. The low power, high performance, dc offset correction circuitry a 9-tap, 18 ps spaced feedforward and feature rich HMC6545 is packaged in a 5 mm 5 mm, equalizer (FFE) a summing node and a linear programmable 32-lead LFCSP package. The device uses a single 3.3 V supply, output driver. The input AGC linearly attenuates or amplifies eliminating external regulators. The HMC6545 operates over a the distorted input signal to generate a constant voltage at the 40C to +95C temperature range. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20152016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. CAGC0 CAGC1 VCC0 VCC1 COMPP0 COMPP1 COMPN1 COMPN0 RST SDA REGSEL1 SCL REGSEL0 SVCC VCC0 VCC1 13393-001 9 32 10 31 30 11 12 29 13 28 27 14 15 26 25 16HMC6545 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ..............................................8 Applications ....................................................................................... 1 Theory of Operation ...................................................................... 11 Functional Block Diagram .............................................................. 1 Input Receiver ............................................................................. 11 General Description ......................................................................... 1 FFE Delay Line ........................................................................... 11 Revision History ............................................................................... 2 Output Driver ............................................................................. 12 Specif icat ions ..................................................................................... 3 2-Wire Serial Port ....................................................................... 12 DC Electrical Characteristics ...................................................... 3 Register Map ................................................................................... 15 AC Electrical Characteristics ...................................................... 3 Register List Summary and Register Descriptions ................ 15 Absolute Maximum Ratings ............................................................ 5 Evaluation Printed Circuit Board (PCB) ..................................... 21 ESD Caution .................................................................................. 5 Evaluation Kit Contents ............................................................ 21 Pin Configuration and Function Descriptions ............................. 6 Outline Dimensions ....................................................................... 23 Interface Schematics..................................................................... 7 Ordering Guide .......................................................................... 23 REVISION HISTORY 6/2016Rev. A to Rev. B Changes to Table 6 .......................................................................... 12 Changes to Table 13 ........................................................................ 15 Changes to Figure 35 ...................................................................... 22 10/2015Revision A: Initial Version Rev. B Page 2 of 23