High Performance, 3.2 GHz, 14-Output Jitter Attenuator with JESD204B Data Sheet HMC7044 FEATURES APPLICATIONS Ultralow rms jitter: 44 fs typical (12 kHz to 20 MHz) at JESD204B clock generation 2457.6 MHz Cellular infrastructure (multicarrier GSM, LTE, W-CDMA) Noise floor: 156 dBc/Hz at 2457.6 MHz Data converter clocking Low phase noise: 141.7 dBc/Hz at 800 kHz, 983.04 MHz output Microwave baseband cards Up to 14 LVDS, LVPECL, or CML type device clocks (DCLKs) Phase array reference distribution from PLL2 GENERAL DESCRIPTION Maximum CLKOUTx/CLKOUTx and SCLKOUTx/SCLKOUTx The HMC7044 is a high performance, dual-loop, integer-N frequency up to 3200 MHz jitter attenuator capable of performing reference selection and JESD204B-compatible system reference (SYSREF) pulses generation of ultralow phase noise frequencies for high speed data 25 ps analog, and VCO cycle digital delay independently converters with either parallel or serial (JESD204B type) interfaces. programmable on each of 14 clock output channels The HMC7044 features two integer mode PLLs and overlapping SPI-programmable phase noise vs. power consumption on-chip VCOs that are SPI-selectable with wide tuning ranges SYSREF valid interrupt to simplify JESD204B synchronization around 2.5 GHz and 3 GHz, respectively. The device is designed to Narrow-band, dual core VCOs meet the requirements of GSM and LTE base station designs and Up to 2 buffered voltage controlled oscillator (VCXO) outputs offers a wide range of clock management and distribution Up to 4 input clocks in LVDS, LVPECL, CMOS, and CML modes features to simplify baseband and radio card clock tree designs. Frequency holdover mode to maintain output frequency The HMC7044 provides 14 low noise and configurable outputs Loss of signal (LOS) detection and hitless reference switching 4 GPIOs alarms/status indicators to determine the health of to offer flexibility in interfacing with many different components the system including data converters, field-programmable gate arrays External VCO input to support up to 6000 MHz (FPGAs), and mixer local oscillators (LOs). On-board regulators for excellent PSRR The DCLK and SYSREF clock outputs of the HMC7044 can be 68-lead, 10 mm 10 mm LFCSP VQ configured to support signaling standards, such as CML, LVDS, LVPECL, and LVCMOS, and different bias settings to offset varying board insertion losses. FUNCTIONAL BLOCK DIAGRAM OSCIN CPOUT1 OSCIN CPOUT2 OSCOUT1 OSCOUT1 CLKOUT0 CLKOUT0 CLKIN0/RFSYNCIN SCLKOUT1 CLKIN0/RFSYNCIN SCLKOUT1 CLKIN1/FIN CLKOUT2 CLKIN1/FIN PLL1 PLL2 CLKOUT2 CLKIN2/OSCOUT0 SCLKOUT3 SCLKOUT3 CLKIN2/OSCOUT0 CLKIN3 CLKIN3 CLKOUT12 CLKOUT12 SCLKOUT13 SCLKOUT13 SYSREF SYNC CONTROL 14-CLOCK SPI DISTRIBUTION CONTROL SDATA INTERFACE SLEN SCLK Figure 1. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. Tel: 781.329.4700 20152021 Analog Devices, Inc. All rights reserved. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 13033-001HMC7044 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 23 Applications ...................................................................................... 1 Detailed Block Diagram ............................................................ 24 General Description ......................................................................... 1 Dual PLL Overview .................................................................... 25 Functional Block Diagram .............................................................. 1 Component BlocksInput PLL (PLL1) ................................. 25 Table of Contents ............................................................................. 2 Component BlocksOutput PLL (PLL2) .............................. 30 Revision History ............................................................................... 2 Clock Output Network .............................................................. 31 Specifications .................................................................................... 3 Reference Buffer Details ............................................................ 38 Conditions ..................................................................................... 3 Typical Programming Sequence .............................................. 38 Supply Current ............................................................................. 3 Power Supply Considerations .................................................. 39 Digital Input/Output (I/O) Electrical Specifications .............. 4 SeriaL Control Port ........................................................................ 42 PLL1 Characteristics .................................................................... 5 Serial Port Interface (SPI) Control .......................................... 42 PLL2 Characteristics .................................................................... 7 Applications Information ............................................................. 43 VCO Characteristics .................................................................... 8 PLL1 Noise Calculations ........................................................... 43 Clock Output Distribution Characteristics .............................. 9 PLL2 Noise Calculations ........................................................... 43 Spur Characteristics ................................................................... 10 Phase Noise Floor and Jitter ..................................................... 43 Noise and Jitter Characteristics ................................................ 10 Control Registers ............................................................................ 44 Clock Output Driver Characteristics ....................................... 11 Control Register Map ................................................................ 44 Absolute Maximum Ratings ......................................................... 13 Control Register Map Bit Descriptions ................................... 52 ESD Caution................................................................................ 13 Evaluation PCB Schematic ............................................................ 69 Pin Configuration and Function Descriptions .......................... 14 Evaluation PCB........................................................................... 69 Typical Performance Characteristics ........................................... 17 Outline Dimensions ....................................................................... 71 Typical Application Circuits ......................................................... 21 Ordering Guide .......................................................................... 71 Terminology .................................................................................... 22 REVISION HISTORY 9/2021Rev. B to Rev. C Changes to Table 49 ....................................................................... 57 Change to Bit 5, Register 0x0001, Table 25................................. 44 Change to Table 75 ........................................................................ 68 Change to Bit 5, Register 0x0001, Table 27................................. 52 5/2016Rev. 0 to Rev. A 11/2016Rev. A to Rev. B Changes to Table 3 ............................................................................ 4 Changes to Table 1 and Endnote 4, Table 2 ................................. 3 Changes to Current Range (ICP2) Parameter, Table 5 ................... 8 Changes to Reliable Signal Swing Parameter, Table 4 ................ 5 Changes to Table 9 ......................................................................... 11 Change to PLL2 VCXO Input Parameter, Table 5 ...................... 7 Changes to Table 10 ....................................................................... 13 Changes to Table 7 ........................................................................... 9 Changes to LDOBYP5 Pin Description ...................................... 15 Added Figure 13 Renumbered Sequentially .............................. 18 Changes to Figure 13 ..................................................................... 19 Added Figure 20 ............................................................................. 19 Changes to Figure 30 ..................................................................... 25 Added Figure 21, Figure 22, and Figure 23 ................................ 20 Changes to Evaluation PCB Section ............................................ 69 Changes to Figure 34 ..................................................................... 21 Added Figure 46 Renumbered Sequentially .............................. 69 Changes to Table 15 and Table 17 ............................................... 34 Added Figure 50 ............................................................................. 71 Changes to Figure 47 ..................................................................... 37 Updated Outline Dimensions ...................................................... 71 Changes to Table 23 ....................................................................... 41 Changes to Table 25 ....................................................................... 46 9/2015Revision 0: Initial Version Rev. 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