0.6 GHz to 3.0 GHz, 0.5 dB LSB, 6-Bit, Silicon Digital Step Attenuator Data Sheet HMC8073 FEATURES FUNCTIONAL BLOCK DIAGRAM HMC8073 Attenuation range: 0.5 dB LSB steps to 31.5 dB Low insertion loss 1.1 dB to 1.0 GHz 1.5 dB to 2.0 GHz VDD 1 12 LE Tight attenuation accuracy LOGIC A0 2 11 GND CONTROL Less than 0.25 dB (plus 3% of attenuation state) GND 3 10 GND Low phase shift error: 4 phase shift to 1.0 GHz 6-BIT DSA 4 9 RFIN RFOUT Bidirectional use: 30 dBm high power handling Internal dc block on the RFIN/RFOUT pins High linearity P1dB: 31 dBm typical Figure 1. Input IP3: 52 dBm typical Safe state transitions Serial interface with TTL/CMOS Up to 8 devices on a single data bus Single-supply operation: 3.3 V to 5.0 V ESD sensitivity rating: Class 1C (1 kV human body model) 2 16-lead, 3 mm 3 mm LFCSP package: 9 mm APPLICATIONS Cellular infrastructure Microwave radios Very small aperture terminals Test equipment and sensors GENERAL DESCRIPTION The HMC8073 is a 6-bit digital step attenuator (DSA), operating The external address feature of the HMC8073 allows users to from 0.6 GHz to 3.0 GHz, that features 31.5 dB of attenuation control up to eight DSAs using a single bus. The DSA has an range with 0.5 dB steps. on-chip regulator that supports a wide supply operating range from 3.3 V to 5.0 V with no performance change in electrical The HMC8073 is implemented in a silicon process, offering characteristics. The HMC8073 incorporates a complementary a fast settling time, low power consumption, and high metal-oxide semiconductor (CMOS)- and transistor transitory electrostatic discharge (ESD) robustness. The device features logic (TTL)- compatible interface that supports serial (3-wire) safe state transitions, allowing attenuation state changes without control of the attenuator. overshooting, and is optimized for excellent step accuracy and high power and high linearity over frequency and temperature The HMC8073 comes in an RoHS compliant, compact, range. The radio frequency (RF) input and output are internally 3 mm 3 mm LFCSP package. matched to 50 and do not require any external matching components. The design is bidirectional, and the RF input and output are interchangeable. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. Tel: 781.329.4700 20182020 Analog Devices, Inc. All rights reserved. No license is granted by implication or otherwise under any patent or patent rights of Analog Technical Support www.analog.com Devices. Trademarks and registered trademarks are the property of their respective owners. GND A2 GND A1 GND SI CLK GND 14678-001 5 16 6 15 7 14 8 13HMC8073 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Insertion Loss, Return Loss, State Error, Normalized Attenuation, Step Error, and Relative Phase .............................7 Applications ...................................................................................... 1 Input Power Compression and Third-Order Intercept ..........9 Functional Block Diagram .............................................................. 1 Theory of Operation ...................................................................... 10 General Description ......................................................................... 1 Power-Up Sequence ................................................................... 10 Revision History ............................................................................... 2 RF Input and Output ................................................................. 10 Specifications .................................................................................... 3 Serial Control Interface ............................................................. 10 Electrical Specifications ............................................................... 3 Attenuation State at Power-Up ................................................ 10 Timing Specifications .................................................................. 4 Applications Information ............................................................. 12 Absolute Maximum Ratings ........................................................... 5 Evaluation PCB........................................................................... 12 Thermal Resistance ...................................................................... 5 Packaging and Ordering Information ......................................... 13 ESD Caution.................................................................................. 5 Outline Dimensions ................................................................... 13 Pin Configuration and Function Descriptions ............................ 6 Ordering Guide .......................................................................... 13 Interface Schematics .................................................................... 6 Typical Performance Characteristics ............................................. 7 REVISION HISTORY 4/2020Rev. A to Rev. B Changes to Figure 1 .......................................................................... 1 Changes to Figure 3 and Table 5 .................................................... 6 Change to Figure 25 ....................................................................... 12 4/2018Revision 0: Initial Version Rev. B Page 2 of 13