Fractional-N PLL with Integrated VCO 25 MHz to 3000 MHz Data Sheet HMC832 FEATURES FUNCTIONAL BLOCK DIAGRAM LD/SDO SCK SDI RF bandwidth: 25 MHz to 3000 MHz HMC832 LOCK 3.3 V supply DETECT Maximum phase detector rate: 100 MHz SPI SEN CONTROL PROGRAMMING Ultralow phase noise INTERFACE 110 dBc/Hz in band, typical EN Fractional figure of merit (FOM): 226 dBc/Hz MODULATOR CAL RF P 24-bit step size, resolution 3 Hz typical EN RF N Exact frequency mode with 0 Hz frequency error Fast frequency hopping 1, 2, 4, 6, ...62 2 40-lead 6 mm 6 mm SMT package: 36 mm APPLICATIONS N VCO Cellular infrastructure CP CP PFD VTUNE Microwave radio R WiMax, WiFi Communications test equipment CATV equipment XREFP DDS replacement Figure 1. Military Tunable reference source for spurious-free performance GENERAL DESCRIPTION The HMC832 is a 3.3 V, high performance, wideband, frac- The HMC832 is footprint-compatible to the market leading tional-N, phase-locked loop (PLL) that features an integrated HMC830 PLL with integrated VCO. It features 3.3 V supply and voltage controlled oscillator (VCO) with a fundamental an innovative programmable performance technology that enables frequency of 1500 MHz to 3000 MHz, and an integrated VCO the HMC832 to tailor current consumption and corresponding output divider (divide by 1/2/4/6/60/62), that enables the noise floor performance to individual applications by selecting HMC832 to generate continuous frequencies from 25 MHz to either a low current consumption mode or a high performance mode for an improved noise floor performance. 3000 MHz. The integrated phase detector (PD) and delta-sigma (-) modulator, capable of operating at up to 100 MHz, permit Additional features of the HMC832 include 12 dB of RF output wider loop bandwidths and faster frequency tuning with gain control in 1 dB steps output mute function to automatically excellent spectral performance. mute the output during frequency changes when the device is Industry leading phase noise and spurious performance, across not locked selectable output return loss programmable all frequencies, enable the HMC832 to minimize blocker effects, differential or single-ended outputs, with the ability to select and to improve receiver sensitivity and transmitter spectral either output in single-ended mode and a - modulator exact purity. A low noise floor (160 dBc/Hz) eliminates any contri- frequency mode that enables users to generate output frequencies with 0 Hz frequency error. bution to modulator/mixer noise floor in transmitter applications. Rev. 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Technical Support www.analog.com 12827-001HMC832 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 PLL Register Map ........................................................................... 36 Applications ....................................................................................... 1 ID, Read Address, and RST Registers ...................................... 36 Functional Block Diagram .............................................................. 1 Reference Divider, Integer, and Fractional Frequency Registers ....................................................................................... 36 General Description ......................................................................... 1 VCO SPI Register ....................................................................... 37 Revision History ............................................................................... 2 Delta-Sigma Configuration ....................................................... 37 Specif icat ions ..................................................................................... 3 Lock Detect Register .................................................................. 38 Timing Specifications .................................................................. 5 Analog Enable (EN) Register .................................................... 38 Absolute Maximum Ratings ............................................................ 6 Charge Pump Register ............................................................... 39 Recommended Operating Conditions ...................................... 6 Autocalibration Register ............................................................ 39 ESD Caution .................................................................................. 6 Phase Detector (PD) Register ................................................... 40 Pin Configuration and Function Descriptions ............................. 7 Exact Frequency Mode Register ............................................... 40 Typical Performance Characteristics ............................................. 8 General-Purpose, Serial Port Interface, and Reference Theory of Operation ...................................................................... 14 Divider (GPO SPI RDIV) Register ........................................ 41 PLL Subsystem Overview .......................................................... 14 VCO Tune Register .................................................................... 42 VCO Subsystem Overview ........................................................ 14 SAR Register ............................................................................... 42 SPI (Serial Port Interface) Configuration of PLL and VCO General-Purpose 2 Register ...................................................... 42 Subsystems ................................................................................... 14 Built-In Self Test Register .......................................................... 42 VCO Subsystem .......................................................................... 16 VCO Subsystem Register Map ...................................................... 43 PLL Subsystem ............................................................................ 20 VCO Enable Register ................................................................. 43 Soft Reset and Power-On Reset ................................................ 28 VCO Output Divider Register .................................................. 44 Power-Down Mode .................................................................... 29 VCO Configuration Register .................................................... 44 General-Purpose Output (GPO) Pin ....................................... 29 VCO Calibration/Bias, CF Calibration, and MSB Calibration Chip Identification ..................................................................... 29 Registers ....................................................................................... 45 Serial Port .................................................................................... 29 VCO Output Power Control ..................................................... 45 Applications Information .............................................................. 33 Evaluation Printed Circuit Board (PCB) ..................................... 46 Power Supply ............................................................................... 34 Changing Evaluation Board Reference Frequency and CP Programmable Performance Technology................................ 34 Current Configuration .............................................................. 46 Loop Filter and Frequency Changes ........................................ 34 Evaluation Kit Contents ............................................................ 46 RF Programmable Output Return Loss ................................... 35 Outline Dimensions ....................................................................... 47 Mute Mode .................................................................................. 35 Ordering Guide .......................................................................... 48 REVISION HISTORY 11/14Rev. 0 to Rev. A This Hittite Microwave Products data sheet has been reformatted to meet the styles and standards of Analog Devices, Inc. Updated Format .................................................................. Universal Moved Endnotes from Typical Performance Characteristics Section to the Applications Information Section ....................... 34 Changes to Ordering Guide .......................................................... 48 Rev. A Page 2 of 48