HMC905LP3E v01.0414 6 GHz LOW NOISE PROGRAMMABLE DIVIDER (N = 1 to 4) Typical Applications Features The HMC905LP3E is ideal for: Low Noise Floor: 4 4 -164 dBc/Hz at 10 MHz Offset for N = 4 LO Generation with Low Noise Floor Programmable Frequency Divider, N = 1, 2, 3 or 4 Software Defined Radios 400 MHz to 6 GHz Input Frequency Range Clock Generators Up to +6 dBm Output Power Fast Switching Synthesizers Sleep Mode: Consumes <1 A Military Applications 2 16 Lead 3X3 mm SMT Package: 9mm Test Equipment Sensors Functional Diagram General Description The HMC905LP3E is a SiGe BiCMOS low noise programmable frequency divider in a 3x3 mm lead- less surface mount package. The circuit can be pro- grammed to divide from N = 1 to N = 4 in the 400 MHz to 6 GHz input frequency range. The high level out- put power (up to 6 dBm single ended) with a very low SSB phase noise and 50% duty cycle makes this device ideal for low noise clock generation, LO generation and LO drive applications. Configurable bias and output power controls allow current consumption and output power control. The device incorporates a power down feature, good input to output isolation and fast start up time. The HMC905LP3E can be included into fast switching ping-pong applications. Electrical Specifications, T = +25 C, Vcc = +3.3V, Z = 50 o A Parameter Conditions Min. Typ. Max. Units RF Input Characteristics 1 RF Input Frequency Single-ended input 400 6000 MHz RF Input Power Single-ended input 0 6 10 dBm Divider Output Characteristics -Typically, 50 ohms load resistors connected to Vcc Output Power (Single-ended Out) -2 3 6 dBm 2 - 1 bit programmable (CTRL digital signal) SSB Phase Noise 10 kHz Offset -150 dBc/Hz +6 dBm Input Power, 6 GHz input, SSB Phase Noise 100 kHz Offset -158 dBc/Hz 3 Single-Ended Input and Output, Divide-by-4 SSB Phase Noise 10 MHz Offset -164 dBc/Hz Start Up Time EN bit from OFF to ON State (0V to Vcc) 200 ns Power Down Time EN bit from ON to OFF State (Vcc to 0V) 20 ns Delay from divide ratio change Setting Time at Division Ratio Change 25 ns to output frequency change 1 Maximum 5500 MHz in Divide by 2. 2 See typical supply currents vs. BIAS0, BIAS1, CTRL bits table 3 See Residual Phase Noise plot Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, delivery, and to place orders: Analog Devices, Inc., For price, delivery and to place orders: Hittite Microwave Corporation, 20 Alpha Road, Chelmsford, MA 01824 responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Phone: 781-329-4700 Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 4 - 1 Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 1-800-ANALOG-D Application Support: Phone: 978-250-3343 or apps hittite.com FREQUENCY DIVIDERS & DETECTORS - SMT FREQUENCY DIVIDERS & DETECTORS - SMTHMC905LP3E v01.0414 6 GHz LOW NOISE PROGRAMMABLE DIVIDER (N = 1 to 4) Electrical Specifications, T = +25 C, Vcc = +3.3V, Z = 50 (Continued) o A Parameter Conditions Min. Typ. Max. Units 4 4 Isolation SE Input to SE Output EN bit OFF -80 -30 dBc Duty Cycle for Differential Mode 50 % Logic Inputs VIH Input High Voltage 1.5 3.3 V VIL Input Low Voltage 0 0.8 V Power Supplies Analog Supply Vcc (Low Noise LDO for good phase noise - 3.15 3.3 3.45 V HMC860LP3E) Current Consumption 1 Total current vs. BIAS and CTRL bits 82 100 125 mA Sleep Current EN = 0V 1 A 1 The bias bits combination BIAS1 BIAS0 = 1 1 is not recommended All data plots taken on Evaluation Board (schematic on page 10) single-ended with the unused output port 50 ohms terminated, Vcc = +3.3V, Ta=+25 C, except stated otherwise Residual Phase Noise 2 Input Sensitivity Window Divide by 1, 2, 3 & 4 10 -110 Recommended 5 -120 Div By 1 Operating Window Div By 2 Div By 3 0 -130 Div By 4 -5 -140 -10 -150 BIAS1BIAS0=01 BIAS1BIAS0=00 -15 -160 BIAS1BIAS0=10 Operating Window -20 -170 4 5 6 7 8 01 234 56 7 10 100 1000 10 10 10 10 10 INPUT FREQUENCY (GHz) OFFSET FREQUENCY (Hz) Phase Noise for 3 Cascaded Output Phase Noise vs. Input Power HMC905LP3E from 6 GHz VCO Divide-by-4 -10 -90 -100 -30 VCO IN -110 -50 Div By 4 Div By 16 -120 -70 Div By 64 -90 -130 -110 -140 Source IN Div By 4 0dBm -130 -150 Div By 4 3dBm Div By 4 6dBm -150 -160 Div By 4 9dBm -170 -170 4 5 6 7 4 5 6 7 1000 10 10 10 10 10 100 1000 10 10 10 10 OFFSET FREQUENCY (Hz) OFFSET FREQUENCY (Hz) 2 Fin = 6 GHz, Pin = 6 dBm, CTRL = 1, BIAS1 BIAS0 = 01 Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, delivery, and to place orders: Analog Devices, Inc., For price, delivery and to place orders: Hittite Microwave Corporation, 20 Alpha Road, Chelmsford, MA 01824 responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Phone: 781-329-4700 Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 4 - 2 Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 1-800-ANALOG-D Application Support: Phone: 978-250-3343 or apps hittite.com FREQUENCY DIVIDERS & DETECTORS - SMT SSB PHASE NOISE (dBc/Hz) INPUT POWER (dBm) SSB PHASE NOISE (dBc/Hz) SSB PHASE NOISE (dBc/Hz) FREQUENCY DIVIDERS & DETECTORS - SMT