0.1 GHz to 50 GHz, GaAs, MMIC Reflective SPDT Switch Data Sheet HMC986A FEATURES FUNCTIONAL BLOCK DIAGRAM RFC Broadband frequency range: 0.1 GHz to 50 GHz Reflective 50 design Low insertion loss: 2.3 dB at 50 GHz High isolation: 30 dB at 50 GHz High input linearity RF1 RF2 1 dB power compression (P1dB): 28 dBm typical Third-order intercept (IP3): 40 dBm typical High power handling 27 dBm through path V1 V2 13-pad, 0.98 mm 0.75 mm 0.1 mm, CHIP Figure 1. APPLICATIONS Test instrumentation Microwave radios and very small aperture terminals (VSATs) Military radios, radars, and electronic counter measures (ECMs) Broadband telecommunications systems GENERAL DESCRIPTION The HMC986A is a reflective, single-pole, double throw (SPDT) This switch operates with two negative logic control voltages switch, manufactured using a gallium arsenide (GaAs) process. from 5 V to 3 V. All electrical performance data is acquired This switch typically provides low insertion loss of 2.3 dB and with the RFx pads of the HMC986A connected to 50 high isolation of 30 dB in broadband frequency range from transmission lines via one 3.0 mil 0.5 mil ribbon bond of 0.1 GHz to 50 GHz. minimal length. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2019 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 13606-001HMC986A Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ..............................................6 Applications ....................................................................................... 1 Insertion Loss, Return Loss, and Isolation ................................6 Functional Block Diagram .............................................................. 1 Input Power Compression (P1dB) and Third-Order Intercept (IP3) ................................................................................................7 General Description ......................................................................... 1 Theory of Operation .........................................................................9 Revision History ............................................................................... 2 Applications Information .............................................................. 10 Specifications ..................................................................................... 3 Mounting and Bonding Techniques ........................................ 10 Absolute Maximum Ratings ............................................................ 4 Assembly Diagram ..................................................................... 10 Power Derating Curve ................................................................. 4 Outline Dimensions ....................................................................... 11 ESD Caution .................................................................................. 4 Ordering Guide .......................................................................... 11 Pin Configuration and Function Descriptions ............................. 5 Interface Schematics..................................................................... 5 REVISION HISTORY 7/2019Rev. A to Rev. B Deleted Figure 1 Renumbered Sequentially ................................. 1 Added Figure 1 Renumbered Sequentially .................................. 1 Changes to Features Section and General Description Section .... 1 Changes to Specifications Section and Table 1 ............................. 3 Added Figure 2, Thermal Resistance Section, and Table 3 Renumbered Sequentially ................................................................ 4 Changes to Table 2 ............................................................................ 4 Added Figure 3, Figure 4, and Figure 5 ......................................... 5 Changes to Table 4 ............................................................................ 5 Added Figure 6 to Figure 9 .............................................................. 6 Added Figure 10 to Figure 15 ............................................................. Rev. B Page 2 of 11