LTC6950 1.4GHz Low Phase Noise, Low Jitter PLL with Clock Distribution Fea T Descrip T n Low Phase Noise and Jitter The LTC 6950 is a low phase noise integer-N frequency n Additive Jitter: 18fs (12kHz to 20MHz) synthesizer core with clock distribution. The LTC6950 RMS n Additive Jitter: 85fs (10Hz to Nyquist) delivers the low phase noise clock signals demanded in RMS n EZSync Multichip Clock Edge Synchronization high frequency, high resolution data acquisition systems. n Full PLL Core with Lock Indicator The frequency synthesizer contains a full low noise PLL core n 226dBc/Hz Normalized In-Band Phase Noise Floor with a programmable reference divider (R), a programmable n 274dBc/Hz Normalized 1/f Phase Noise feedback divider (N), a phase/frequency detector (PFD) n 1.4GHz Maximum VCO Input Frequency and a low noise charge pump (CP). The clock distribution n Four Independent, Low Noise 1.4GHz LVPECL Outputs section of the LTC6950 delivers up to five outputs based on n One LVDS/CMOS Configurable Output the VCO input. Each output is individually programmed to n Five Independently Programmable Dividers Covering divide the VCO input frequency by any integer from 1 to 63 All Integers from 1 to 63 and to delay the output by 0 to 63 VCO clock cycles. Four n Five Independently Programmable VCO Clock Cycle of the outputs feature very low noise, low skew LVPECL Delays Covering All Integers from 0 to 63 logic signals capable of operation up to 1.4GHz. The fifth n 40C to 105C Junction Temperature Range output is selectable as either an LVDS (800MHz) or CMOS (250MHz) logic type. This output is also programmed to a T produce an output signal based on either the VCO input or the reference divider output. n Clocking High Speed, High Resolution ADCs, L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and EZSync DACs and Data Acquisition Systems and ClockWizard are trademarks of Linear Technology Corporation. All other trademarks are n Low Jitter Clock Generation and Distribution the property of their respective owners. Protected by U.S. Patents, including 8,319,551 and 8,819,472. Typical a T 3.3V 5V 1F 1F 0.1F 100MHz REF 1GHz VCSO OSC + + + V V REF LTC6950 CRYSTEK CP 49.9 CVCSO-914-1000 R DIVIDER 37.4 PECLx Closed-Loop Phase Noise, 0.1F REF PHASE CHARGE CP FREQUENCY PUMP f = 1GHz, Mx 5:0 = 8, 8.2nF DETECTOR VCSO N DIVIDER 422 150 150 49.9 f = 125MHz PECLx 0.1F 100 0.01F 49.9 + NOTES 8, 11, 15 VCO 0.1F RMS JITTER = 93fs 110 VCO (INTEGRATED 100Hz TO 62.5MHz) 49.9 f = 100MHz PFD + 0.01F 120 PECL0 LOOP BW = 12kHz DELAY DIVIDE PECL0 49.9 130 0 TO 63 1 TO 63 SYNC 49.9 SYNC CONTROL + PECL1 140 DELAY DIVIDE 0.01F STAT2 PECL1 0 TO 63 1 TO 63 150 TO STAT1 + ADC OR PECL2 160 TO/FROM DAC DELAY DIVIDE SDO PROCESSOR PECL2 0 TO 63 1 TO 63 SERIAL 170 SDI PORT + PECL3 180 SCLK DELAY DIVIDE 100 1k 10k 100k 1M 10M PECL3 0 TO 63 1 TO 63 CS OFFSET FREQUENCY (Hz) 6950 TA01b + LV/CM DELAY DIVIDE TO FPGA LV/CM 0 TO 63 1 TO 63 GND 6950 TA01a 6950f 1 For more information www.linear.com/LTC6950 ABSOLUTE PHASE NOISE (dBc/Hz) ion pplica ions pplica ion uresLTC6950 a T e Maxi Mu M r a T p c F T (Note 1) TOP VIEW Supply Voltages + + + + + V , V , V , V , V , P0 P1 P2 P3 + + V , and V to GND .....................................3.6V VCO REF 48 47 46 45 44 43 42 41 + V to GND .............................................................5.5V CP + + V 1 40 CP P3 CP Voltage .................................. 0.3V to (V + 0.3V) CP + V PECL3 2 39 + CP CS, SCLK, SDI, SDO, SYNC, VCO , VCO , + PECL3 3 38 GND + + REF , REF , Voltage ........................0.3V to (V + 0.3V) + + V 4 37 V P3 + + + + PECL3 , PECL3 , PECL2 , PECL2 , PECL1 , V 5 36 V P2 VCO + + + PECL1 , PECL0 , PECL0 , LV/CM , LV/CM , PECL2 6 35 VCO + + VCO PECL2 7 34 STAT2, STAT1 .................................................. (Note 28) + + V 8 33 V P2 49 VCO Operating Junction Temperature Range, T (Note 2) J + GND + V 9 32 V P1 LTC6950I ........................................... 40C to 105C PECL1 10 31 GND Junction Temperature, T ................................ 150C JMAX + PECL1 11 30 SYNC Storage Temperature Range .................. 65C to 150C + 12 29 STAT1 V P1 + V 13 28 STAT2 P0 PECL0 14 27 SDI + PECL0 15 26 SCLK + + V 16 25 V P0 17 18 19 20 21 22 23 24 UHH PACKAGE 48-LEAD (5mm 9mm) PLASTIC QFN T = 150C, = 2C/W, = 12C/W JMAX JCbottom JCtop EXPOSED PAD (PIN 49) IS GND, MUST BE SOLDERED TO PCB o r D i n F Ma T LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION JUNCTION TEMPERATURE RANGE LTC6950IUHH PBF LTC6950IUHH TRPBF 6950 48-Lead (5mm 9mm) Plastic QFN 40C to 105C Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on nonstandard lead based finish parts. For more information on lead free part marking, go to: