I (A) CHANNEL 1 TEMP (C) IN1 V (V) OUT1 I (A) OUT1 LTM4678 Dual 25A or Single 50A Module Regulator with Digital Power System Management FEATURES DESCRIPTION n Dual Digitally Adjustable Analog Loops with Digital The LTM 4678 is a dual 25A or single 50A step-down Interface for Control and Monitoring Module (power module) DC/DC regulator featuring n Wide Input Voltage Range: 4.5V to 16V remote configurability and telemetry-monitoring of power n Output Voltage Range: 0.5V to 3.4V management parameters over PMBusan open standard 2 n 0.5% Maximum DC Output Error Over Temperature I C-based digital interface protocol . The LTM4678 n 3.5% Current Readback Accuracy, 20C to 125C is comprised of digitally programmable analog control n Sub-Milliohm DCR Current Sensing loops, precision mixed-signal circuitry, EEPROM, power n Integrated Input Current Sense Amplifier MOSFETs, inductors and supporting components. 2 n 400kHz PMBus-Compliant I C Serial Interface The LTM4678s 2-wire serial interface allows outputs to n Supports Telemetry Polling Rates up to 125Hz be margined, tuned and ramped up and down at program- n Integrated 16-Bit ADC mable slew rates with sequencing delay times. True input n Constant Frequency Current Mode Control current sense, output currents and voltages, output power, n Parallel and Current Share Up to 250A temperatures, uptime and peak values are readable. Custom n 16mm 16mm 5.86mm CoP-BGA Package configuration of the EEPROM contents is not required. At Readable Data start-up, output voltages, switching frequency, and channel n Input and Output Voltages, Currents, and Temperatures phase angle assignments can be set by pin-strapping resis- n Running Peak Values, Uptime, Faults and Warnings tors. The LTpowerPlay GUI and DC1613 USB-to-PMBus n Onboard EEPROM Fault Log Record converter and demo kits are available. Writable Data and Configurable Parameters n Output Voltage, Voltage Sequencing and Margining The LTM4678 is offered in a 16mm 16mm 5.86mm n Digital Soft-Start/Stop Ramp, Program Analog Loop CoP-BGA package available with SnPb or RoHS compliant n OV/UV/OT, UVLO, Frequency and Phasing terminalfinish. All registered trademarks and trademarks are the property of their respective owners. Protected by U.S. Patents including 5408150, 5481178, 5705919, 5929620, 6144194, 6177787, 6580258, APPLICATIONS 7420359, 8163643. Licensed under U.S. Patent 7000125 and other related patents worldwide. n System Optimization, Characterization and Data Min- ing in Prototype, Production and Field Environments TYPICAL APPLICATION Dual 25A Module Regulator with Digital Using PMBus and LTpowerPlay to Monitor Telemetry and Margin Interface for Control and Monitoring* V /V During Load Pattern Tests, 10Hz Polling Rate, 12V OUT0 OUT1 IN V OUT0 Output Voltage Readback, V Margined 7.5% Low Input Current Readback OUT 4.5V to 16V + ADJUSTABLE V (FROM OUT0 1.1 1.9 2.6 4.3 IN UP TO 25A + 4.5V TO 5.75V, V OSNS0 R CONNECT SENSE 1.0 1.8 1.0 1.6 22F 100F LOAD0 IN V , SV 8 IN IN 5 V OSNS0 AND INTV V 0.9 1.7 0.5 0.8 CC IN1 V TOGETHER) OUT1 V IN0 V OUT1 ADJUSTABLE 0.8 1.6 0 0 SV IN + V OSNS1 UP TO 25A 0 3 6 9 12 0 3 6 9 12 RUN1 LTM4678 100F LOAD1 TIME (SEC) 4678 TA01b TIME (SEC) 4678 TA01d ON/OFF CONTROL 8 RUN0 V OSNS1 Output Current Readback, Varying Load Pattern Power Stage Temperature Readback FAULT0 25 25 60 60 FAULT INTERRUPTS FAULT1 2 I C/SMBus I/F WITH PMBus SCL 10 10 57 57 SYNC COMMAND SET TO/FROM SDA SYNCHRONIZATION TIME-BASE IPMI OR OTHER BOARD SHARE CLK REGISTER WRITE PROTECTION ALERT MANAGEMENT CONTROLLER 5 5 54 54 WP SGND GND 4678 TA01a 0 0 51 51 *FOR COMPLETE CIRCUIT, SEE FIGURE 46 0 3 6 9 12 0 3 6 9 12 TIME (SEC) 4678 TA01c TIME (SEC) 4678 TA01e Rev. A 1 Document Feedback For more information www.analog.com V (V) I (A) OUT0 OUT0 CHANNEL 0 TEMP (C) I (A) IN0LTM4678 TABLE OF CONTENTS Features ..................................................... 1 FSWPH CFG Pin Strapping Look-Up Table to Set Applications ................................................ 1 the LTM4678s Switching Frequency and Channel Phase-Interleaving Angle (Not Applicable if Typical Application ........................................ 1 MFR CONFIG ALL 6 = 1b) ...................................31 Description.................................................. 1 ASEL Pin Strapping Look-Up Table to Set the Table of Contents .......................................... 2 LTM4678s Slave Address (Applicable Regardless Absolute Maximum Ratings .............................. 4 of MFR CONFIG ALL 6 Setting) ..........................32 Order Information .......................................... 4 LTM4678 MFR ADDRESS Command Examples Pin Configuration .......................................... 4 Expressed in 7- and 8-Bit Addressing ....................32 Electrical Characteristics ................................. 5 Fault Detection and Handling ...................................32 Typical Performance Characteristics .................. 12 Status Registers and ALERT Masking ....................33 Pin Functions .............................................. 15 Mapping Faults to FAULT Pins ...............................35 Simplified Block Diagram ............................... 19 Power Good Pins ...................................................35 Decoupling Requirements ............................... 19 CRC Protection ......................................................35 Functional Diagram ...................................... 20 Serial Interface .........................................................35 Test Circuits ............................................... 21 Communication Protection ....................................35 Operation................................................... 22 Device Addressing ...................................................35 Power Module Introduction .....................................22 Responses to V and I /I Faults ....................36 OUT IN OUT Power Module Overview, Major Features ..................22 Output Overvoltage Fault Response .......................36 EEPROM with ECC ...................................................23 Output Undervoltage Response .............................37 Power-Up and Initialization ...................................... 24 Peak Output Overcurrent Fault Response ..............37 Soft-Start .................................................................25 Responses to Timing Faults .....................................37 Time-Based Sequencing ..........................................25 Responses to V OV Faults .....................................37 IN Voltage-Based Sequencing ......................................25 Responses to OT/UT Faults ......................................37 Shutdown ................................................................26 Internal Overtemperature Fault Response ..............37 Light-Load Current Operation ..................................26 External Overtemperature and Undertemperature Switching Frequency and Phase ...............................27 FaultResponse ....................................................38 PWM Loop Compensation .......................................27 Responses to Input Overcurrent and Output Output Voltage Sensing ...........................................27 Undercurrent Faults ...............................................38 INTV /EXTV Power ............................................27 CC CC Responses to External Faults ...................................38 Output Current Sensing and Sub Milliohm DCR Fault Logging ...........................................................38 Current Sensing .....................................................28 Bus Timeout Protection ...........................................38 Input Current Sensing ..............................................28 2 Similarity Between PMBus, SMBus and I C PolyPhase Load Sharing ..........................................28 2-Wire Interface .....................................................39 External/Internal Temperature Sense .......................29 PMBus Serial Digital Interface .................................39 RCONFIG (Resistor Configuration) Pins ...................29 Abbreviations of Supported Data Formats ...............40 VOUTn CFG Pin Strapping Look-Up Table for the Figure 7 to Figure 24 PMBus Protocols .................. 41 LTM4678s Output Voltage, Coarse Setting (Not PMBus Command Summary ............................ 44 Applicable if MFR CONFIG ALL 6 = 1b) ...............29 PMBus Commands ..................................................44 VTRIMn CFG Pin Strapping Look-Up Table for the PMBus Commands Summary (Note: The Data LTM4678s Output Voltage, Fine Adjustment Setting FormatAbbreviations are Detailed in Table 8) ........44 (Not Applicable if MFR CONFIG ALL 6 = 1b) ......30 Data Format Abbreviations ......................................49 Rev. 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