EVALUATION KIT AVAILABLE MAX11270 24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma ADC with Integrated PGA General Description Features and Benefits The MAX11270 is a 24-bit delta-sigma ADC that achieves High Resolution for Instrumentation Applications that excellent 130dB SNR while dissipating an ultra-low 10mW. Require a Wide Dynamic Range Sample rates up to 64ksps allow both precision DC and 130dB SNR at 1.9sps AC measurements. Integral nonlinearity is guaranteed 112dB SNR at 1000sps to 4ppm maximum. The THD is -122dB. The MAX11270 20.4-Bit Noise-Free Resolution at 1.9sps communicates via an SPI-compatible serial interface and 17.4-Bit Noise-Free Resolution at 1000sps is available in a small 24-pin TSSOP package. Longer Battery Life for Portable Applications The MAX11270 offers a 6.5nV/Hz noise programmable 2.4mA Operating Mode Current gain amplifier with gain settings between 1x to 128x. 4.4mA PGA Low-Noise Mode Current Optional buffers are also included to provide isolation of 1A Sleep Current the signal inputs from the switched capacitor sampling High Accuracy for DC Measurements network. This allows the MAX11270 to be used with 1ppm INL (typ), 4ppm (max) high-impedance sources without compromising available Single or Split Analog Supplies Provide Input Voltage dynamic range. Range Flexibility The MAX11270 operates from a single 2.7V to 3.6V 2.7V to 3.6V (Single Supply) or analog supply, or split 1.8V analog supplies, allowing 1.8V (Split Supplies) the analog input to be sampled below ground. The digital Flexible High-Performance Filter Architecture supply range is 2.0V to 3.6V, allowing communication with Simplifies Design 2.5V, 3V, or 3.3V logic. Programmable SINC Filter Applications Enables System Integration Low-Noise PGA with Gains of 1, 2, 4, 8, 16, 32, Scientific Instrumentation 64, 128 High-Precision Portable Sensors Signal Buffer Optional Medical Equipment 3 General-Purpose I/Os ATE Enables Integrated Part and System Calibration for Gain and Offset Ordering Information and Functional Diagram appear at end of data sheet. Robust 24-Pin TSSOP Packaging Typical Application Circuit 2.7V TO 3.6V REF 10nF 2.0V TO 3.6V 1F 1F REFN REFP AVDD DVDD RSTB SYNC AINP CSB C 10nF SCLK MAX11270 C0G DIN DOUT AINN RDYB GPIO3 GPI02 GPI01 CAPP CAPN CAPREG AVSS AVSS DGND 1F 0603 X7R 10nF C0G 19-7048 Rev 1 5/15MAX11270 24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma ADC with Integrated PGA TABLE OF CONTENTS General Description ............................................................................ 1 Applications .................................................................................. 1 Features and Benefits .......................................................................... 1 Typical Application Circuit ....................................................................... 1 Absolute Maximum Ratings ...................................................................... 6 Package Thermal Characteristics ................................................................. 6 Electrical Characteristics ........................................................................ 6 Typical Operating Characteristics ................................................................ 10 Pin Configuration ............................................................................. 14 Pin Description ............................................................................... 14 Functional Diagram ........................................................................... 16 Detailed Description........................................................................... 17 System Clock 17 Voltage Reference Inputs . 17 Analog Inputs 17 Input Buffers . 17 Bypass/Direct Connect 17 Programmable Gain Amplifier (PGA) 17 Input Voltage Range . 18 Noise Performance vs. Data Rate 18 Power-On Reset 23 Power-Down Modes . 23 Digital Filters . 25 SINC Filter . 25 Serial Interface . 25 Chip Select (CSB) 25 SCLK (Serial Clock) . 25 DIN (Serial Data Input) . 25 DOUT (Serial Data Output) . 26 Data Ready (RDYB) . 26 SPI Incomplete Write Command Termination . 26 SPI Incomplete Read Command Termination . 27 SPI Timing Characteristics . 27 Modes and Registers 30 Conversion Mode (MODE = 0) . 30 Register Access Mode (MODE = 1) . 30 Register Map ................................................................................ 31 Maxim Integrated 2 www.maximintegrated.com