EVALUATION KIT AVAILABLE MAX14001/MAX14002 Configurable, Isolated 10-bit ADCs for Multi-Range Binary Inputs General Description Benefits and Features The MAX14001/MAX14002 are isolated, single-channel Enables Robust Detection of Binary Inputs analog-to-digital converters (ADCs) with programmable Programmable Input Bias Current Rejects Line Noise voltage comparators and inrush current control optimized 3.75kV of Isolation for 60 Seconds RMS 5.5mm of Creepage and Clearance for configurable binary input applications. 3.75kV RMS of integrated isolation is provided between the binary Group II CTI Package Material input side (field-side) and the comparator output/SPI-side Reduces BOM and Board Space Through High (logic-side) of the MAX14001/MAX14002. An integrated, Integration isolated, DC-DC converter powers all field-side circuitry, 10-bit, 10ksps ADC and this allows running field-side diagnostics even when Binary Threshold Comparators no input signal is present. The 20-pin SSOP package Control Circuit for Driving a Depletion Mode FET provides 5.5mm of creepage and clearance with group II Isolation for Both Data and DC-DC Supply CTI rating. 20-SSOP Package These devices continually digitize the input voltage on Increases Equipment Up Time and Simplifies the field-side of an isolation barrier and transmit the data System Maintenance across the isolation barrier to the logic-side of the device Enables Field-Side Diagnostics where the magnitude of the input voltage is compared to Automatic Self-Diagnostics programmable thresholds. The binary comparator output Provides Unparalleled Flexibility pin is high when the input voltage is above the upper Programmable Upper and Lower Input Thresholds threshold and low when it is below the lower threshold. Programmable Inrush Current Activation Threshold, Response time of the comparator to an input change Magnitude, and Duration is less than 150s with filtering disabled. With filtering Daisy-Chainable SPI Interface enabled, the comparator uses the moving average of the last 2, 4, or 8 ADC readings. Both filtered and unfiltered Applications ADC readings are available through the 5MHz SPI port, High-Voltage Binary Input (12V300V) which is also used to set comparator thresholds and other Distribution Automation device configuration. Substation Automation The MAX14001/MAX14002 control the current of a binary Industrial Control, Multi-Range, Digital Input Modules input through an external, high-voltage FET. This current with Individually Isolated Inputs cleans relay contacts and attenuates input noise. An inrush Safety Regulatory Approvals comparator monitoring the ADC readings triggers the inrush UL According to UL1577 current, or wetting pulse. The inrush trigger threshold, cur- rent magnitude, and current duration are all programmable Ordering Information appears at end of data sheet. in the MAX14001 but are fixed in the MAX14002. When the high-voltage FET is not providing inrush current, it switches to bias mode. Bias mode places a small current load on the binary input to attenuate capacitively coupled noise. The level of bias current is programmable between 50A and 3.75mA in both the MAX14001 and MAX14002. This allows optimization of the tradeoff between noise attenuation and power dissipation. 19-8514 Rev 1 8/17MAX14001/MAX14002 Configurable, Isolated 10-bit ADCs for Multi-Range Binary Inputs Absolute Maximum Ratings V to GNDL .........................................................-0.3V to +6V V to GNDF ........................................................-0.3V to +6V DDL DDF V to GNDL ..........................................................-0.3V to +6V Short-Circuit Duration DD Logic-Side Inputs (CS, SCLK, SDI, FAULT) to GNDL (FAULT, COUT, SDO to GNDL or V ) ................Continuous DD ................................................................................ -0.3V to +6V Continuous Power Dissipation (T = +70C) A Logic-Side Outputs (SDO, COUT) 20-pin SSOP ..............................................................952.4mW to GNDL .............................................. -0.3V to (V + 0.3V) Operating Temperature Range ......................... -40C to +125C DDL V , V to AGND ...........................................-0.3V to +2V Junction Temperature ......................................................+150C REFIN AIN AGND to GNDF ....................................................-0.3V to +0.3V Storage Temperature Range ............................ -65C to +150C GATE to GNDF ........................................................-0.3V to +4V Lead Temperature (soldering, 10s) .................................+300C IFET to GNDF .......................................................-0.3V to +12V Soldering Temperature (reflow) .......................................+260C ISET to GNDF .........................................................-0.3V to +2V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Package Thermal Characteristics (Note 1) 20-pin SSOP Junction-to-Ambient Thermal Resistance ( ) ..........84C/W JA Junction-to-Case Thermal Resistance ( ) ...............32C/W JC Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial. Electrical Characteristics (V - V = 1.71V to 5.5V, V - V = 3.0V to 3.6V, R = 120k, T = -40C to +125C, V = V . Typical values DDL GNDL DD GNDL ISET A GNDF GNDL are at T = +25C with V = V = +3.3V, R = 120k, V = V .) (Notes 2, 3) A DDL DD ISET GNDF GNDL PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER SUPPLIES Logic Power Supply V 1.71 5.5 V DDL Logic Supply Current I V = 3.3V, no load, CS = high 0.7 1.5 mA DDL DDL Isolated DC-DC Power V 3.0 3.3 3.6 V DD Supply Input Voltage Isolated DC-DC Supply I V = 3.3V 4.8 8 mA DD DD Input Current Logic Power-Up Delay 0.2 ms Field Power-Up Delay C = 0.1F 1 ms VDDF Field Power Supply V C = 0.1F, unregulated output voltage 2.5 3.0 3.5 V DDF VDDF Gate Charge Pump V 1A pull-down 3 3.6 4 V GATE Voltage V V 3V 1.5 1.6 1.66 V Logic-Side Undervoltage UVLOL DD Lockout Threshold V V 1.71V 2.69 2.82 2.95 V UVLOD DDL Logic-Side Undervoltage V 50 mV UVLHYST Lockout Threshold V 100 mV Hysteresis UVDHYST Field-Side Undervoltage V (Note 4) 1.95 2.1 2.25 V UVLOF Lockout Threshold Maxim Integrated 2 www.maximintegrated.com