19-6331 Rev 0 5/12 MAX14850PMB1 Peripheral Module General Description Features The MAX14850PMB1 peripheral module utilizes the S Isolates SPI- or UART-Based Pmod-Compatible MAX14850 digital isolator to isolate another SPI- or UART- Modules from the Host System K based module from any host system that utilizes Pmod - S Data Rates from 2Mbps to 20Mbps or Greater, compatible expansion ports configurable for either a UART Depending on Configuration or SPI interface. This peripheral module is first plugged S 2-Pin Header to Connect External Voltage for into the host Pmod port. Another UART- or SPI-based Isolated Module module plugged into the 12-pin Pmod-compatible S 600V Isolation for 60s connector on this peripheral module is galvanically isolated RMS from the host and referenced to a secondary power supply S Isolates Four SPI or UART Signals and Two connected to this peripheral module. Control Signals The IC is a 6-channel digital isolator utilizing Maxims pro- S Short-Circuit Protection on Unidirectional Outputs prietary process technology, whose monolithic design S 12-Pin Pmod-Compatible Male Connector to Host provides a compact and low-cost transfer of digital S 12-Pin Pmod-Compatible Female Connection for signals between circuits with different power domains. Of Module to be Isolated the six total channels, the four unidirectional channels are each capable of DC to 50Mbps, with two of the four chan- S RoHS Compliant nels passing data across the isolation barrier in each S Proven PCB Layout direction. The two bidirectional channels are open drain S Fully Assembled and Tested and each is capable of data rates from DC to 2Mbps. Refer to the MAX14850 IC data sheet for detailed informa- tion regarding operation of the IC. Ordering Information appears at end of data sheet. MAX14850PMB1 Peripheral Module Pmod is a trademark of Digilent Inc. Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxims website at www.maxim-ic.com.MAX14850PMB1 Peripheral Module Component List DESIGNATION QTY DESCRIPTION DESIGNATION QTY DESCRIPTION 12-pin (2 x 6) right-angle female 0.1FF Q10%, 16V X7R ceramic J2 1 header C1, C2 2 capacitors (0603) Murata GRM188R71C104KA01D J3 1 2-pin straight male header R1R6 6 150I Q5% resistors (0603) 1FF Q10%, 10V X7R ceramic C3 1 capacitor (0603) R7R10 4 4.7kI Q5% resistors (0603) TDK C1608X7R1A105K 6-channel digital isolator (16 SO) U1 1 Maxim MAX14850ASE+ 12-pin (2 x 6) right-angle male J1 1 header 1 PCB: EPCB14850PM1 Component Suppliers SUPPLIER PHONE WEBSITE Murata Electronics North America, Inc. 770-436-1300 www.murata-northamerica.com TDK Corp. 847-803-6100 www.component.tdk.com Note: Indicate that you are using the MAX14850PMB1 when contacting these component suppliers. Table 1. Connector J1 (with SPI/UART Detailed Description Peripheral Attached to J2) UART Interface PIN SIGNAL DESCRIPTION The MAX14850PMB1 peripheral module can interface 1 SS CTS Serial select/clear to send to the host by plugging directly into a Pmod-compatible 2 MOSI TXD Master-out slave input/host transmit port (configured for SPI or UART) through connector J1. See Table 1. 3 MISO RXD Master-in slave output/host receive 4 SCK RTS Serial clock/ready to send Connector J2 provides the galvanically isolated connec- tion to another peripheral module. Note that even though 5 GND Ground the pinout numbering is different than J1, the signals from 6 VCC Power supply the top row of pins on J1 are passed through to the top 7 SPAREIN Spare input from Pmod to host row of pins on J2. See Table 2. 8 N.C. Not connected Connector J3 provides power from the 2nd power domain 9 N.C. Not connected to the isolated side of the IC and the isolated Pmod. 10 SPAREIO Spare input/output 11 GND Ground Software and FPGA Code Example software and drivers are available that execute 12 VCC Power supply directly without modification on several FPGA devel- opment boards that support an integrated or synthe- ity, and uses an API interface (maximDeviceSpecific sized microprocessor. These boards include the Digilent Utilities.c) to set and access Maxim device functions Nexys 3, Avnet LX9, and Avnet ZEDBoard, although within a specific module. other platforms can be added over time. Maxim provides complete Xilinx ISE projects containing HDL, Platform The source code is written in standard ANSI C format, and Studio, and SDK projects. In addition, a synthesized bit all API documentation including theory/operation, register stream, ready for FPGA download, is provided for the description, and function prototypes are documented in demonstration application. the API interface file (maximDeviceSpecificUtilities.h & .c). The software project (for the SDK) contains several The complete software kit is available for download at source files intended to accelerate customer evalu- www.maxim-ic.com. Quick start instructions are also ation and design. These include a base application available as a separate document. (maximModules.c) that demonstrates module functional- Maxim Integrated Products 2