EVALUATION KIT AVAILABLE MAX5857 16-Bit, 5.9Gsps Wideband Interpolating and Modulating RF DAC with JESD204B Interface General Description Benefits and Features The MAX5857 high-performance, interpolating and modulating, Simplifies RF Design and Enables New 16-bit, 5.9Gsps RF DAC can directly synthesize up to Communication Architectures 1.2GHz of instantaneous bandwidth from DC to Eliminates I/Q Imbalance and LO Feedthrough frequencies greater than 2.6GHz. The device is optimized Enables Multi-Band RF Modulation for cable access and digital video broadcast applications Direct RF Synthesis of 1.2GHz Bandwidth and meets spectral emission requirements for a broad set 5.898Gsps DAC Output Update Rate of radio transmitters and modulators including DOCSIS High-Performance 14-Bit RF DAC Core 3.1/3.0, DVB-C2, DVB-T2, DVB-S2X, ISDB-T, and EPoC. Digital Baseband I/Q with 4x Interpolation The device integrates interpolation filters, a digital quadra- Bypass Path Without Interpolation for Real RF ture modulator, a numerically controlled oscillator (NCO), Digital Quadrature Modulator+NCO for Full Agility clock multiplying PLL+VCO and a 14-bit RF DAC core. The Sub-1Hz NCO Resolution 4x linear phase interpolation filter simplifies reconstruction Integrated Clock Multiplying PLL+VCO filtering, while enhancing passband dynamic performance Highly Flexible and Configurable and reducing the input data bandwidth required from an 3, 4, 5, or 6-Lane JESD204B Input Data Interface FPGA. The NCO allows for fully agile modulation of the Subclass-0 Compliant input baseband signal for direct RF synthesis. The complex Up to 9.8304Gbps Per Lane Divided Reference Clock Output data path can be bypassed to access the RF DAC core directly. SPI Interface for Device Configuration The MAX5857 input interface accepts 16-bit input data Applications through a six-lane JESD204B SerDes data input interface DOCSIS 3.1 Remote PHY and CCAP that is Subclass-0. The interface can be configured for 3, Digital Video Broadcast Modulators 4, 5, or 6 lanes and supports data rates up to 9.8304Gbps DVB-C2/DVB-T2/DVB-S2X/ISDB-T to optimize the I/O lane count and speed. Ethernet PON Over Coax (EPoC) The MAX5857 clock input has a flexible interface that Point-to-Point Wireless accepts a differential sine-wave or square-wave input Instrumentation clock signal up to 5.9GHz. A bypassable clock multiplying PLL and VCO can be used to internally generate the high- Simplified Block Diagram frequency sampling clock using a reference frequency between 245.76MHz and 1.475GHz. The device provides PLL COMP VCOBYP a divided reference clock to ensure synchronization MAX5857 CLKP PLL CLOCK RCLKP between the data source and the DAC. CLKN N DISTRIBUTION RCLKN The integrated RF DAC uses a differential current- 14 steering architecture that includes a differential 50 6 DP 5:0 MUTE DN 5:0 16 internal termination and can produce a 3.2dBm full-scale 4 JESD 14-BIT output signal level on a 50 external load. Operating OUTP 14 204B 5.9Gsps SYNCNP from 1.0V and 1.8V power supplies, the device consumes OUTN RF DAC 16 SYNCNN 2.7W at 4.9Gsps. The device is offered in a compact 144- 4 MOD pin, 10mm x 10mm, FCCSP pack age and is specified for the extended industrial temperature range (-40C to INTB REFERENCE Reference Quadrature QUADRATURE SPI PORT SPI Port SYSTEM NCO System NCO RESETB +85C). Ordering Information appears at end of data sheet. 19-100283 Rev 0 3/18 VDD AVDD AVCLK GND CSBP REFIO MUX FSADJ DACREF MUX CSB SCLK SDI SDOMAX5857 16-Bit, 5.9Gsps Wideband Interpolating and Modulating RF DAC with JESD204B Interface TABLE OF CONTENTS General Description ............................................................................ 1 Simplified Block Diagram........................................................................ 1 Absolute Maximum Ratings ...................................................................... 9 Package Information ........................................................................... 9 Electrical Characteristics ........................................................................ 9 Typical Operating Characteristics ................................................................ 15 Pin Configuration ............................................................................. 18 Pin Description ............................................................................... 19 Functional Diagram ........................................................................... 21 Detailed Description........................................................................... 22 JESD204B Interface . 23 Supported DAC Update Rate and JESD204B Data Rates . 23 JESD204B Data Interface Features 25 Mapping of Physical to Logical Channels 25 Mapping of Bypass Mode Data 25 High-Speed Input Receiver (Rx) . 25 JESD204B Receiver Equalization 28 Lane Skew Requirement . 28 Link Layer (LINK) . 29 Interface Timing for Subclass-0 30 Serial Control Interface . 31 Interrupt Control 35 Digital Control Pins 37 Frequency Planning . 38 Quadrature Modulator and NCO 38 Analog Interface 41 Reference Interface . 41 Analog Output . 42 Clock Interface . 43 Clock Subsystem . 43 Overview . 43 DAC Clock PLL 44 VCO Band Select . 45 Lock Detect . 45 PLL External Components 45 RCLK Description and Use . 45 Interpolation Filters 45 Maxim Integrated 2 www.maximintegrated.com