MAX5868 16-Bit, 5Gsps Interpolating and Modulating RF DAC General Description Features and Benefits The MAX5868 high-performance interpolating and modu- Direct RF Synthesis Solution for Communications lating 16-bit 5Gsps RF DAC can directly synthesize up to 4.96Gsps DAC Output Update Rate 500MHz of instantaneous bandwidth from DC to frequen- High-Performance 14-Bit RF DAC Core Digital Quadrature Modulator and NCO with cies greater than 2GHz. The device is optimized for cable and digital video broadcast applications and meets spec- 1Hz/10Hz/100Hz/1kHz/10kHz Resolution 4x/5x/6x/8x/10x/12x/16x/20x/24x Interpolation tral mask requirements for a broad set of communication standards including EPoC, DVB-T, DVB-T2, DVB-C2, 16-Bit 1240Mwps DDR Parallel LVDS Data Bus ISDB-T, and DOCSIS 3.0/3.1. Highly Flexible and Configurable Data Bus with Word, Byte and Nibble Modes The device integrates interpolation filters, a digital quadra- ture modulator, a numerically controlled oscillator (NCO) Reference Clock Output for FPGA Interface Multiple DAC Synchronization and a 14-bit RF DAC core. The user-configurable 4x, 5x, SPI Interface for Device Configuration 6x, 8x, 10x, 12x, 16x, 20x or 24x, linear phase interpola- tion filters reduce the input data bandwidth required from Low Power, Compact Solution an FPGA/ASIC. The NCO allows for fully agile modulation 1.5W at f = 5Gsps CLK of the input baseband signal for direct RF synthesis. 10mm x 10mm, 144-Pin CSBGA The MAX5868 includes a source synchronous 16-bit Applications parallel LVDS data input interface. The input baseband Ethernet PON over Coax (EPoC) I and Q signals are time interleaved on a single parallel Downstream DOCSIS CMTS Modulators input port configured for double data rate clocking at up to Digital Video Broadcast 1240Mwps (620Mwps I and Q each). The device accepts DVB-T / DVB-T2 / DVB-C2 / ISDB-T Modulators data in word (16 bit), byte (8 bit), or nibble (4 bit) modes. The input data is aligned to the data clock supplied with the data. An input FIFO decouples the timing of the input Simplified Block Diagram interface from the DAC update clock domain. In addition, a parity input and parity flag interrupt output are available to ensure data integrity. RCLKP RCLKN MAX5868 CLKP The MAX5868 clock input has a flexible clock interface CLOCK CLKN DISTRIBUTION and accepts a differential sine-wave or square-wave input clock signal. The device outputs a divided reference clock SYNCIP MUTE MOD SYNCIN to ensure synchronization with the FPGA/ASIC driving its 16 R DP 15:0 input port. In addition, dedicated input and output signals OUTP DN 15:0 14-BIT 14 are provided for synchronizing multiple devices. FIFO/ 5Gsps DCLKP RF DAC OUTN SYNC DCLKN The MAX5868 uses a differential current-steering archi- 16 R PARP SYNCOP tecture and can produce a 0dBm full-scale output signal PARN SYNC SYNCON SYNC level with a 50 load. Operating from 1.8V and 1.0V INTB REFERENCE QUADRATURE SPI power supplies, the device consumes 1.5W at 5Gsps. SYSTEM PORT NCO RESETB The device is offered in a compact 144-pin CSBGA pack- age and is specified for the extended temperature range (-40C to +85C). For related parts and recommended products to use with this part, refer Ordering Information appears at end of data sheet. to www.maximintegrated.com/MAX5868.related. 19-6746 Rev 1 6/14 VDD AVDD AVCLK GND CSBP REFIO FSADJ DACREF CSB SCLK SDI SDOMAX5868 16-Bit, 5Gsps Interpolating and Modulating RF DAC Absolute Maximum Ratings AVDD2, AVCLK2, V ........................................-0.3V to +2.1V AVDD, AVCLK, V .............................................-0.3V to +1.2V DD2 DD OUTP, OUTN ...................................... -0.3V to (V + 0.5V) REFIO, DACREF, AVDD2 MUTE, RESETB, CSB, SCLK, FSADJ, CSBP ................0.3V to (V + 0.3V, MAX 2.1V) AVDD2 SDO, SDI, INTB................. -0.3V to (V + 0.3V, 2.1V Max) CLKP, CLKN ....................-0.3V to (V + 0.3V, MAX 2.1V) DD2 AVCLK2 SINCIP, SYNCIN, SYNCOP, SYNCON, DCLKP, DCLKN, Continuous Power Dissipation (T = +70C) A RCLKP, RCLKN ................. -0.3V to (V + 0.3V, 2.1V Max) CSBGA (derate 38.8mW/C above +70C) ...............3101mW DD2 DP0, DN0, DP1, DN1, DP2, DN2, DP3, DN3, SDO, INTB Maximum Continuous Current ..........................8mA DP4, DN4 ......................... -0.3V to (V + 0.3V, 2.1V Max) Operating Temperature Range DD2 DP5, DN5, DP6, DN6, DP7, DN7, DP8, DN8, T ................................................................... -40C to +85C A DP9, DN9 .......................... -0.3V to (V + 0.3V, 2.1V Max) T .................................................................. -40C to +125C DD2 J DP10, DN10, DP11, DN11, DP12, DN12, DP13, Junction Temperature ......................................................+150C DN13................................. -0.3V to (V + 0.3V, 2.1V Max) Storage Temperature Range ............................ -60C to +150C DD2 DP14, DN14, DP15, DN15, Soldering Temperature (reflow) .......................................+260C PARP, PARN ........................0.3V to (V + 0.3V, 2.1V Max) DD2 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Package Thermal Characteristics (Note 1) CSBGA Junction-to-Case Thermal Resistance ( ) ............12.9C/W JC Junction-to-Board Thermal Resistance ( ) ...........6.23C/W JB Junction-to-Ambient Thermal Resistance ( ) .......25.8C/W JA Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial. Electrical Characteristics (V V = V = 1.0V, V = V = V = 1.8V, P = 0dBm, 10x interpolation, 16-bit word mode, AVDD = AVCLK DD AVDD2 AVCLK2 DD2 CLK I = 29.5385mA, output is 50 double-terminated and transformer coupled, external reference at 1.20V, R = 1.3k between OUTFS SET FSADJ and DACREF. T = -40C, T = +115C, unless otherwise noted. Typical values are at T = +60C.) (Note 2) A(MIN) J(MAX) J PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE Input Data Word Width 16 Bits DAC Resolution 14 Bits Differential Nonlinearity DNL Figure 4 1.5 LSB Integral Nonlinearity INL Figure 4 3 LSB Offset Voltage Error OS 0.003 %FS Full-Scale Output Current Range I 10 30 mA OUTFS Output Voltage Gain Error GE f = DC, Figure 4 3 %FS FS OUT Output Power P f = 100MHz, f = 4.96GHz 0 dBm OUT OUT CLK Typical maximum single-ended output Maximum Output Compliance V + 0.4 V AVDD2 voltage Typical minimum single-ended output Minimum Output Compliance V - 0.4 V AVDD2 voltage Output Resistance R Differential DAC output resistance 50 OUT Maxim Integrated 2 www.maximintegrated.com