EVALUATION KIT AVAILABLE Click here for production status of specific part numbers. MAX5871 16-Bit, 5.9Gsps Interpolating and Modulating RF DAC with JESD204B Interface General Description Benefits and Features The MAX5871 high-performance interpolating and modu- Simplifies RF Design and Enables New Wireless lating 16-bit 5.9Gsps RF DAC can directly synthesize Communication Architectures up to 600MHz of instantaneous bandwidth from DC to Eliminates I/Q Imbalance and LO Feedthrough frequen cies greater than 2.8GHz. The device enables Enables Multi-Band RF Modulation multi-standard and multi-band transmitters in wireless Direct RF Synthesis of 600MHz Bandwidth Up to 2.8GHz communications applications. The device meets spectral 5.898Gsps DAC Output Update Rate mask requirements for a broad set of communication High-Performance 14-Bit RF DAC Core standards including multicarrier GSM, UMTS, and LTE. Digital Quadrature Modulator and NCO with The device integrates interpolation filters, a digital quadra- 1Hz/10Hz/100Hz/1kHz/10kHz Resolution ture modulator, a numerically controlled oscillator (NCO), 5x/6x/6.67x/8x/10x/12x/13.33x/16x/20x/24x clock multiplying PLL+VCO and a 14-bit RF DAC core. Interpolation The user-configurable 5x, 6x, 6.67x, 8x, 10x, 12x, 13.33x, Integrated Clock Multiplying PLL+VCO 16x, 20x or 24x, linear phase interpola tion filters sim- Highly Flexible and Configurable plify reconstruction filtering, while enhancing passband 1, 2, or 4-Lane JESD204B Input Data Interface dynamic performance, and reduce the input data band- Subclass-0 and Subclass-1 Compliant width required from an FPGA/ASIC. The NCO allows for Up to 10Gbps Per Lane fully agile modulation of the input baseband signal for Reference Clock for System Synchronization direct RF synthesis. Multiple DAC Synchronization (Subclass-1) The MAX5871 accepts 16-bit input data via a four-lane SPI Interface for Device Configuration JESD204B SerDes data input interface that is Subclass-0 and Subclass-1 compliant. The interface can be config- Applications ured for 1, 2, or 4 lanes and supports data rates up to Cellular Base-Station Transmitters 10Gbps per lane allowing flexibility to optimize the I/O 2.5G/3G - GSM/TDMA/CDMA/UMTS count and speed. 4G LTE and WiMAX Multi-Standard and Multi-Band Transmitters The MAX5871 clock input has a flexible clock interface Point-to-Point Microwave Links and accepts a differential sine-wave, or square-wave Wireless Backhaul input clock signal. A bypassable clock multiplying PLL and VCO can be used to generate a high-frequency sam- Simplified Block Diagram pling clock. The device outputs a divided reference clock to ensure synchronization of the system clock and DAC PLL COMP VCOBYP clock. In addition, multiple devices can be synchronized MAX5871 CLKP CLOCK RCLKP using JESD204B Subclass-1. PLL DISTRIBUTION RCLKN CLKN The MAX5871 uses a differential current-steering archi- MOD SYSREFP tecture and can produce a 0dBm full-scale output signal 16 MUTE SYSREFN R level with a 50 load. Operating from 1.8V and 1.0V 4 14 14-BIT OUTP DP 3:0 JESD SYNC 5.9Gsps power supplies, the device consumes 2.5W at 4.9Gsps. DN 3:0 204B OUTN RF DAC 16 The device is offered in a compact 144-pin, 10mm x R SYNCNP SYNCOP SYNC 10mm, FCCSP pack age and is specified for the extended SYNCNN SYNCON industrial temperature range (-40C to +85C). INTB REFERENCE QUADRATURE SPI PORT SYSTEM NCO RESETB Ordering Information appears at end of data sheet. 19-7462 Rev 1 7/19 VDD AVDD AVCLK GND CSBP REFIO MUX FSADJ DACREF CSB SCLK SDI SDOMAX5871 16-Bit, 5.9Gsps Interpolating and Modulating RF DAC with JESD204B Interface TABLE OF CONTENTS General Description ............................................................................ 1 Benefits and Features .......................................................................... 1 Applications .................................................................................. 1 Simplified Block Diagram........................................................................ 1 Absolute Maximum Ratings ...................................................................... 6 Package Thermal Characteristics ................................................................. 6 Electrical Characteristics ........................................................................ 6 Typical Operating Characteristics ................................................................ 13 Pin Configuration ............................................................................. 18 Pin Description ............................................................................... 19 Functional Diagram ........................................................................... 21 Detailed Description........................................................................... 22 JESD204B Interface . 23 JESD204B Data Interface Features 24 High-Speed Input Receiver (Rx) . 24 JESD204B Receiver Equalization 26 Synchronization with SYSREF . 27 Link Layer (LINK) . 29 Lane Skew Requirement . 30 Mapping of Physical to Logical Channels 30 Serial Control Interface . 31 Interrupt and Mute . 36 Digital Control Pins 38 Frequency Planning . 38 Signal Bandwidth . 39 Complex Modulator and NCO 39 Analog Interface 41 Reference Interface . 41 Analog Output 41 DAC Clock PLL . 42 VCO Band Select . 44 Lock Detect . 44 PLL External Components 44 Interpolation Filters 44 Maxim Integrated 2 www.maximintegrated.com