MAX7304PMB1 Peripheral Module General Description Features The MAX7304PMB1 peripheral module provides the S Four LED Driver Pins on PORT12PORT15 necessary hardware to interface the MAX7304 16-port S 256-Step PWM Individual LED Intensity-Control GPIO and LED driver to any system that utilizes Accuracy PmodK-compatible expansion ports configurable for S Individual LED Blink Rates and Common LED 2 I C communication. The IC features 16 GPIO ports Fade-In/Out Rates with 12 push-pull GPIOs and four open-drain GPIOs S Individually Programmable GPIOs to Two Logic configurable as PWM-controlled LED drivers. The device Levels supports a 1.62V to 3.6V separate power supply for level S 8-Channel Individual Programmable Level translation. Each GPIO can be programmed to one of Translators the two externally applied logic voltage levels. PORT12 S Configurable Edge-Triggered Port Interrupt PORT15 can also be configured as LED drivers that feature constant-current sinks and PWM intensity control 2 S Jumper-Selectable I C Address Setting with the internal oscillator. The maximum constant- 2 S 6-Pin Pmod-Compatible Connector (I C) current level for each open-drain LED port is 20mA. The S Secondary Header Allows Daisy-Chaining of intensity of the LED on each open-drain port can be indi- 2 Additional Modules on I C Bus vidually adjusted through a 256-step PWM control. The S Example Software Written in C for Portability port also features LED fading. S RoHS Compliant Refer to the MAX7304 IC data sheet for detailed informa- S Proven PCB Layout tion regarding operation of the IC. S Fully Assembled and Tested Ordering Information appears at end of data sheet. MAX7304PMB1 Peripheral Module Pmod is a trademark of Digilent Inc. For pricing, delivery, and ordering information, please contact Maxim Direct at 19-6327 Rev 0 5/12 1-888-629-4642, or visit Maxim Integrateds website at www.maximintegrated.com.MAX7304PMB1 Peripheral Module Component List DESIGNATION QTY DESCRIPTION DESIGNATION QTY DESCRIPTION JP1 1 6-pin (2 x 3) straight male header 1FF Q10%, 10V X7R ceramic C1, C3 2 capacitors (0603) LED1LED4 4 Red LEDs (1206) TDK C1608X7R1A105K R1, R2, R3 3 150I Q5% resistors (0603) R4, R5 2 4.7kI Q5% resistors (0603) 0.1FF Q10%, 16V X7R ceramic C2 1 capacitor (0603) R6 1 10kI Q5% resistor (0603) Murata GRM188R71C104KA01D 16-port, level-translating GPIO J1 1 6-pin right-angle male header U1 1 and LED driver (24 TQFN-EP*) Maxim MAX7304ETG+ 18-pin (2 x 9) straight male J2 1 header 1 Shorting jumper J3 1 8-pin (2 x 4) straight male header 1 PCB: EPCB7304PM1 *EP = Exposed pad. Component Suppliers SUPPLIER PHONE WEBSITE Murata Electronics North America, Inc. 770-436-1300 www.murata-northamerica.com TDK Corp. 847-803-6100 www.component.tdk.com Note: Indicate that you are using the MAX7304PMB1 when contacting these component suppliers. 2 Table 1. Connector J1 (I C Communication) Detailed Description PIN SIGNAL DESCRIPTION UART Interface 1 N.C. Not connected The MAX7304PMB1 peripheral module can interface to 2 INT Interrupt the host by plugging directly into a Pmod-compatible port 2 3 SCL I C serial clock 2 (configured for I C) through connector J1. See Table 1. 2 4 SDA I C serial data The J2 connector provides the connection to the push- 5 GND Ground pull and open-drain outputs. See Table 2. 6 VCC Power supply The J3 connector allows the module to be connected 2 through a daisy-chain from another I C module and/or 2 2 provide I C and power connections to other I C modules The software project (for the SDK) contains several on the same bus. See Table 3. source files intended to accelerate customer evalu- 2 ation and design. These include a base application Jumper JP1 provides the ability to set the I C address. (maximModules.c) that demonstrates module function- This is accomplished by connecting the AD0 pin to GND, ality and uses an API interface (maximDeviceSpecific VCC, SDA, or SCL. See Table 4. Utilities.c) to set and access Maxim device functions Software and FPGA Code within a specific module. Example software and drivers are available that execute The source code is written in standard ANSI C format, and directly without modification on several FPGA devel- all API documentation including theory/operation, register opment boards that support an integrated or synthe- description, and function prototypes are documented in sized microprocessor. These boards include the Digilent the API interface file (maximDeviceSpecificUtilities.h & .c). Nexys 3, Avnet LX9, and Avnet ZEDBoard, although The complete software kit is available for download at other platforms can be added over time. Maxim provides www.maximintegrated.com. Quick start instructions are complete Xilinx ISE projects containing HDL, Platform also available as a separate document. Studio, and SDK projects. In addition, a synthesized bit stream, ready for FPGA download, is provided for the demonstration application. Maxim Integrated 2