Octal Sample-and-Hold a with Multiplexed Input SMP18 FEATURES FUNCTIONAL BLOCK DIAGRAM High Speed Version of SMP08 Internal Hold Capacitors (LSB) (MSB) Low Droop Rate INPUT A B C INH TTL/CMOS Compatible Logic Inputs 3 11 10 9 6 Single or Dual Supply Operation 8 DGND 1 OF 8 DECODER Break-Before-Make Channel Addressing 16 V DD Compatible With CD4051 Pinout SW 13 CH OUT 0 Low Cost APPLICATIONS SW 14 CH OUT 1 Multiple Path Timing Deskew for A.T.E. Memory Programmers SW 15 CH OUT 2 Mass Flow/Process Control Systems Multichannel Data Acquisition Systems SW 12 CH OUT 3 Robotics and Control Systems Medical and Analytical Instrumentation SW 1 CH OUT 4 Event Analysis Stage Lighting Control SW 5 CH OUT 5 GENERAL DESCRIPTION SW 2 CH OUT 6 The SMP18 is a monolithic octal sample-and-hold it has eight internal buffer amplifiers, input multiplexer, and internal hold SW 4 CH OUT 7 capacitors. It is manufactured in an advanced oxide isolated HOLD CAPS CMOS technology to obtain high accuracy, low droop rate, and (INTERNAL) fast acquisition time. The SMP18 has a typical linearity error of 7 V SS only 0.01% and can accurately acquire a 10-bit input signal to SMP18 1/2 LSB in less than 2.5 microseconds. The SMP18s output swing includes the negative supply in both single and dual sup- ply operation. The SMP18 was specifically designed for systems that use a The SMP18 offers significant cost and size reduction over calibration cycle to adjust a multiple of system parameters. The discrete designs. It is available in a 16-pin plastic DIP, a low cost and high level of integration make the SMP18 ideal for narrow body SO-16 surface-mount SOIC package or the thin calibration requirements that have previously required an ASIC, TSSOP-16 package. The SMP18 is a higher speed direct or high cost multiple D/A converters. replacement for the SMP08. The SMP18 is also ideally suited for a wide variety of sample- and-hold applications including amplifier offset or VCA gain ad- justments. One or more SMP18s can be used with single or multiple DACs to provide multiple set points within a system. REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties Tel: 617/329-4700 World Wide Web Site: SMP18SPECIFICATIONS ( V = +5 V, V = 5 V, DGND = 0 V, R = No Load, T = 408C to +858C for SMP18F, DD SS L A ELECTRICAL CHARACTERISTICS unless otherwise noted) Parameter Symbol Conditions Min Typ Max Units Linearity Error 3 V V +3 V 0.01 % IN Buffer Offset Voltage V T = +25C, V = 0 V 2.5 10 mV OS A IN 40C T +85C, V = 0 V 3.5 20 mV A IN Hold Step V V = 0 V, T = +25C to +85C 46mV HS IN A V = 0 V, T = 40C8mV IN A Droop Rate V /tT = +25C, V = 0 V 2 40 mV/s CH A IN 1 Output Source Current I V = 0 V 1.2 mA SOURCE IN 1 Output Sink Current I V = 0 V 0.5 mA SINK IN Output Voltage Range R = 20 k 3.0 +3.0 V L LOGIC CHARACTERISTICS Logic Input High Voltage V 2.4 V INH Logic Input Low Voltage V 0.8 V INL Logic Input Current I V = 2.4 V 0.5 1 A IN IN 2 DYNAMIC PERFORMANCE 3 Acquisition Time t T = +25C, 3 V to +3 V to 0.1% 3.5 s AQ A Hold Mode Settling Time t To 1 mV of Final Value 1 s H Channel Select Time t 90 ns CH Channel Deselect Time t 45 ns DCS Inhibit Recovery Time t 90 ns IR Slew Rate SR 6 V/s Capacitive Load Stability <30% Overshoot 500 pF Analog Crosstalk 3 V to +3 V Step 72 dB SUPPLY CHARACTERISTICS Power Supply Rejection Ratio PSRR V = 5 V to 6 V 60 75 dB SS Supply Current I T = +25C 5.5 7.5 mA DD A 40C T +85C 7.5 9.5 mA A ( V = +12 V, V = 0 V, DGND = 0 V, R = No Load, T = 408C to +858C for SMP18F, DD SS L A ELECTRICAL CHARACTERISTICS unless otherwise noted) Parameter Symbol Conditions Min Typ Max Limits Linearity Error 60 mV V 10 V 0.01 % IN Buffer Offset Voltage V T = +25C, V = 6 V 2.5 10 mV OS A IN 40C T +85C, V = 6 V 3.5 20 mV A IN Hold Step V V = 6 V, T = +25C to +85C 46mV HS IN A V = 6 V, T = 40C8mV IN A Droop Rate V /tT = +25C, V = 6 V 2 40 mV/s CH A IN 1 Output Source Current I V = 6 V 1.2 mA SOURCE IN 1 Output Sink Current I V = 6 V 0.5 mA SINK IN Output Voltage Range R = 20 k 0.06 10.0 V L R = 10 k 0.06 9.5 V L LOGIC CHARACTERISTICS Logic Input High Voltage V 2.4 V INH Logic Input Low Voltage V 0.8 V INL Logic Input Current I V = 2.4 V 0.5 1 A IN IN 2 DYNAMIC PERFORMANCE 3 Acquisition Time t T = +25C, 0 to 10 V to 0.1% 2.5 3.25 s AQ A Hold Mode Settling Time t To 1 mV of Final Value 1 s H Channel Select Time t 90 ns CH Channel Deselect Time t 45 ns DCS Inhibit Recovery Time t 90 ns IR 4 Slew Rate SR 7 V/s Capacitive Load Stability <30% Overshoot 500 pF Analog Crosstalk 0 V to 10 V Step 72 dB SUPPLY CHARACTERISTICS Power Supply Rejection Ratio PSRR 10.8 V V 13.2 V 60 75 dB DD Supply Current I T = +25C 6.0 8.0 mA DD A 40C T +85C 8.0 10.0 mA A NOTES 1 Outputs are capable of sinking and sourcing over 10 mA but offset is guaranteed at specified load levels. 2 All input control signals are specified with t = t = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V. r f 3 This parameter is guaranteed without test. 4 Slew rate is measured in the sample mode with a 0 to 10 V step from 20% to 80%. Specifications subject to change without notice. 2 REV. C