Low Power Audio Codec Data Sheet SSM2603 FEATURES GENERAL DESCRIPTION Stereo, 24-bit analog-to-digital and digital-to-analog converters The SSM2603 is a low power, high quality stereo audio codec DAC SNR: 100 dB (A-weighted), THD: 80 dB at 48 kHz, 3.3 V for portable digital audio applications with one set of stereo ADC SNR: 90 dB (A-weighted), THD: 80 dB at 48 kHz, 3.3 V programmable gain amplifier (PGA) line inputs and one Highly efficient headphone amplifier monaural microphone input. It features two 24-bit analog-to- Stereo line input and monaural microphone input digital converter (ADC) channels and two 24-bit digital-to- Low power analog (DAC) converter channels. 7 mW stereo playback (1.8 V/1.5 V supplies) The SSM2603 can operate as a master or a slave. It supports 14 mW record and playback (1.8 V/1.5 V supplies) various master clock frequencies, including 12 MHz or 24 MHz Low supply voltages for USB devices standard 256 f or 384 f based rates, such as S S Analog: 1.8 V to 3.6 V 12.288 MHz and 24.576 MHz and many common audio sampling Digital core: 1.5 V to 3.6 V rates, such as 96 kHz, 88.2 kHz, 48 kHz, 44.1 kHz, 32 kHz, 24 Digital I/O: 1.8 V to 3.6 V kHz, 22.05 kHz, 16 kHz, 12 kHz, 11.025 kHz, and 8 kHz. 256/384 oversampling rate in normal mode 250/272 over- The SSM2603 can operate at power supplies as low as 1.8 V for sampling rate in USB mode the analog circuitry and as low as 1.5 V for the digital circuitry. Audio sampling rates: 8 kHz, 11.025 kHz, 12 kHz, 16 kHz, The maximum voltage supply is 3.6 V for all supplies. 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, and 96 kHz The SSM2603 software-programmable stereo output options 28-lead, 5 mm 5 mm LFCSP package provide the user with many application possibilities. Its volume control functions provide a large range of gain control of the APPLICATIONS audio signal. Mobile phones The SSM2603 is specified over the industrial temperature range MP3 players of 40C to +85C. It is available in a 28-lead, 5 mm 5 mm Portable gaming lead frame chip scale package (LFCSP). Portable electronics Educational toys FUNCTIONAL BLOCK DIAGRAM AVDD VMID AGND DBVDD DGND DCVDD HPVDD PGND SSM2603 MICBIAS BYPASS 6dB TO 15dB/MUTE 3dB STEP 34.5dB TO +33dB, 73dB TO +6dB, SIDETONE 1.5dB STEP 1dB STEP RHPOUT RLINEIN MUX ADC DAC ROUT DIGITAL MICIN PROCESSOR 0dB/20dB BOOST LOUT MUX ADC DAC LLINEIN LHPOUT 34.5dB TO +33dB, 6dB TO 15dB/MUTE 3dB STEP 73dB TO +6dB, 1.5dB STEP SIDETONE 1dB STEP BYPASS CLK DIGITAL AUDIO INTERFACE CONTROL INTERFACE MCLK/ XTO CLKOUT PBDAT RECDAT BCLK PBLRC RECLRC MUTE CSB SDIN SCLK XTI Figure 1. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20082018 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 07241-001SSM2603 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Digital Audio Interface .............................................................. 15 Applications ....................................................................................... 1 Software Control Interface ........................................................ 17 General Description ......................................................................... 1 Control Register Sequencing .................................................... 17 Functional Block Diagram .............................................................. 1 Typical Application Circuits ......................................................... 18 Revision History ............................................................................... 2 Register Map ................................................................................... 19 Specifications ..................................................................................... 3 Register Map Details ...................................................................... 20 Digital Filter Characteristics ....................................................... 4 Left-Channel ADC Input Volume, Address 0x00 .................. 20 Timing Characteristics ................................................................ 5 Right-Channel ADC Input Volume, Address 0x01 ............... 21 Absolute Maximum Ratings ............................................................ 7 Left-Channel DAC Volume, Address 0x02 ............................. 21 Thermal Resistance ...................................................................... 7 Right-Channel DAC Volume, Address 0x03 .......................... 22 ESD Caution .................................................................................. 7 Analog Audio Path, Address 0x04 ........................................... 22 Pin Configuration and Function Descriptions ............................. 8 Digital Audio Path, Address 0x05 ............................................ 22 Typical Performance Characteristics ............................................. 9 Power Management, Address 0x06 .......................................... 23 Converter Filter Response ........................................................... 9 Digital Audio I/F, Address 0x07 ............................................... 24 Digital De-Emphasis .................................................................. 10 Sampling Rate, Address 0x08 .................................................... 24 Theory of Operation ...................................................................... 11 Active, Address 0x09 .................................................................. 27 Digital Core Clock ...................................................................... 11 Software Reset, Address 0x0F ................................................... 27 ADC and DAC ............................................................................ 11 ALC Control 1, Address 0x10 ................................................... 28 ADC High-Pass and DAC De-Emphasis Filters .................... 11 ALC Control 2, Address 0x11 ................................................... 28 Hardware Mute Pin .................................................................... 11 Noise Gate, Address 0x12 .......................................................... 29 Automatic Level Control (ALC) ............................................... 12 Outline Dimensions ....................................................................... 30 Analog Interface ......................................................................... 13 Ordering Guide .......................................................................... 30 REVISION HISTORY 7/2018Rev. C to Rev. D 8/2009Rev. 0 to Rev. A Change to Features Section ............................................................. 1 Changes to General Description Section and Figure 1 ................ 1 Changes to Figure 6 .......................................................................... 8 Changes to Specifications Section, Table 1 .................................... 3 Updated Outline Dimensions ....................................................... 30 Changes to Master Clock Tolerance, Frequency Range Changes to Ordering Guide .......................................................... 30 Parameter, Table 2 ............................................................................. 4 Added Endnote 1, Table 2 ................................................................ 4 6/2013Rev. B to Rev. C Changes to Table 6 ............................................................................. 6 Changes to Table 8 ............................................................................ 7 Changes to Figure 6 and Table 9 ...................................................... 8 Changes to Digital Core Clock Section ....................................... 11 4/2012Rev. A to Rev. B Changes to Digital Audio Data Sampling Rate Section ............ 15 Changes to Figure 31 ...................................................................... 18 Changes to Figure 1 .......................................................................... 1 Changes to Stereo Line and Monaural Microphone Inputs Added Control Register Sequencing Section.............................. 17 Section and Figure 20 ..................................................................... 13 Change to Table 10 ......................................................................... 19 Changes to Table 10 ........................................................................ 19 Changes to Table 15, Table 16, Table 17, and Table 18 .............. 22 Changes to Table 19 and Table 20 ................................................ 23 Changes to Table 37 ....................................................................... 29 Updated Outline Dimensions ....................................................... 31 Added Exposed Pad Notation to Outline Dimensions ............. 31 Changes to Ordering Guide .......................................................... 31 2/2008Revision 0: Initial Version Rev. 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