TISP61089M PROGRAMMABLE OVERVOLTAGE PROTECTOR DUAL FORWARD-CONDUCTING P-GATE THYRISTOR TISP61089M SLIC Overvoltage Protector High 70 A 5/310 Capability Agency Recognition Dual Voltage-Programmable Protector Description - Supports Voltages Down to -155 V - Low 5 mA max. Gate Triggering Current UL File Number: E215609 - High 150 mA min. Holding Current Description 8 Pin Small-Outline (D008) Package (Top View) The TISP61089M is a dual forward-conducting buffered p-gate K1 1 8 K1 (Tip) (Tip) over-voltage protector. It is designed to protect monolithic SLICs (Subscriber Line Interface Circuits) against overvoltages on 7 G 2 A (Ground) (Gate) the telephone line caused by lightning, a.c. power contact and NC 3 6 A (Ground) induction. The TISP61089M limits voltages that exceed the SLIC supply rail voltage. The TISP61089M parameters are specified to 4 5 (Ring) K2 K2 (Ring) allow equipment compliance with Bellcore GR-1089-CORE, ITU-T MD6XANB K.21 and K.45 and YD/T-950. NC - No internal connection Terminal typical application names shown in The SLIC line driver section is typically powered from 0 V (ground) parenthesis and a negative voltage in the region of -20 V to -155 V. The protector gate is connected to this negative supply. This references Device Symbol the protection (clipping) voltage to the negative supply voltage. As the protection voltage will then track the negative supply voltage, K1 K1 the overvoltage stress on the SLIC is minimized. Positive overvoltages are clipped to ground by diode forward conduction. Negative overvoltages are initially clipped close to the A SLIC negative supply rail value. If sufficient current is available from G the overvoltage, then the protector will crowbar into a low voltage A on-state condition. As the overvoltage subsides, the high holding current of the crowbar helps prevent d.c. latchup. These monolithic protection devices are fabricated in ion-implanted K2 K2 planar vertical power structures for high reliability and in normal system operation they are virtually transparent. The TISP61089M Terminals K1, K2 and A correspond to the alternative buffered gate design reduces the loading on the SLIC supply line designators of T, R and G or A, B and C. The during overvoltages caused by power cross and induction. The negative protection voltage is controlled by the TISP61089M is available in an 8-pin plastic small-outline surface voltage, V , applied to the G terminal. GG mount package. SD6XAEBa How to Order Device PackageCarrier Order As Marking Code Standard Quantity Embossed Tape Reeled TISP61089MDR-S 1089M 2500 TISP61089M 8 Pin Small Outline (D008) SEPTEMBER 2013 REVISED JULY 2019 *RoHS Directive 2015/863, Mar 31, 2015 and Annex. Specifications are subject to change without notice. Users should verify actual device performance in their WARNING Cancer and Reproductive Harm specific applications. The products described herein and this document are subject to specific legal disclaimers as www.P65Warnings.ca.gov set forth on the last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf. TISP61089M SLIC Overvoltage Protector Absolute Maximum Ratings, T = 25 C (Unless Otherwise Noted) J Rating Symbol ValueUnit Repetitive peak off-state voltage, I =0 T = 25 C V -170 V G J DRM Repetitive peak gate-cathode voltage, V =0 T = 25 C V -167 V KA J GKRM Non-repetitive peak on-state pulse current (see Notes 1 and 2) 10/1000 s (Bellcore GR-1089-CORE, Issue 1, November 1994, Section 4) 30 I A 5/310 s (ITU-T K.20/21/45, YD/T-950, open-circuit voltage wave shape 10/700 s) 70 TSP 2/10 s (Bellcore GR-1089-CORE) 120 Non-repetitive peak on-state current, 60Hz (see Notes 1 and 2 and Figure 2 on Page 4) 0.1s 11 1 s 4.5 I A TSM 5 s 2.4 300 s 0.95 900 s 0.93 Junction temperature T -40 to +150 C J Storage temperature range T -40 to +150 C stg NOTES:1.Initially the protector must be in thermal equilibrium with T = 25 C. The surge may be repeated after the device returns to its J initial conditions. 2. The rated current values may be applied either to the Ring to Ground or to the Tip to Ground terminal pairs. Additionally, both terminal pairs may have their rated current values applied simultaneously (in this case the Ground terminal current will be twice the rated current value of an individual terminal pair). Recommended Operating Conditions MinTyp MaxUnit C Gate decoupling capacitor 100 nF G Electrical Characteristics, T = 25 C (Unless Otherwise Noted) J ParameterTest Conditions MinTyp MaxUnit T = 25 C-5 A J I Off-state current V =V , V =0 D D DRM GK T =85 C-50 A J 2/10s, I =-100 A, di/dt = -80 A/s, R =50 , V =-100 V, TM S GG V Breakover voltage -112 V (BO) (see Note 4) V Forward voltageI =5 A, t =200s3 V F F w Peak forward recovery V 2/10s, I =100 A, di/dt = 80A/s, R =50 , (see Note 4) 10 V FRM F S voltage I Holding currentI =-1A, di/dt = 1A/ms, V =-100 V-150 mA H T GG T = 25 C-5 A J I Gate reverse current V =V =V , V =0 GAS GG GK GKRM KA T =85 C-50 A J I =-3A, t 20s, V =-48 V5 mA I Gate trigger current T p(g) GG GT V Gate trigger voltage I =-3A, t 20s, V =-48 V2.5 V GT T p(g) GG V =-3V 100 pF D Anode-cathode off-state C f= 1MHz, V =1 V, I =0, (see Note 3) AK d G capacitance V =-48 V50pF D NOTE:3.These capacitance measurements employ a three terminal capacitance bridge incorporating a guard circuit. The unmeasured device terminals are a.c. connected to the guard terminal of the bridge. NOTE:4.Voltage measurements should be made with an oscilloscope with limited bandwidth (20 MHz) to avoid high frequency noise. SEPTEMBER 2013 REVISED JULY 2019 Specifications are subject to change without notice. Users should verify actual device performance in their specific applications. The products described herein and this document are subject to specific legal disclaimers as set forth on the last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf.