ACCL-9410 High Speed Quad-Channel 3/1 Digital Isolator Data Sheet Description Features ACCL-9410 is a quad-channel bi-directional digital isolator. Supply voltage: 3.3 V / 5 V Using capacitive coupling through an insulation barrier, the Wide operating temperature: -40 C to 125 C isolator enables high speed digital transmissions. The device is High data rate: 25 MBd capable of running at 25 MBd data rate, with propagation delay Low power consumption: 2 mA per channel of 40ns. Low propagation delay: 40 ns max ACCL-9410 is available in 150mils narrow body 16-pin SOIC Pulse width distortion: 8 ns max package. The isolator operates at 3.3V/5V supply. The electrical Propagation delay part skew: 15 ns max DC and timing AC specifications are specified over the Propagation delay channel skew: 8 ns max temperature range of -40C to +125C. Output enable function Safety and Regulatory Approvals (Pending) Functional Diagram UL 1577 V 1 16 DD1 V DD2 Applications GND 2 15 GND 1 2 Industrial control isolated data interfaces, eg SPI High speed digital systems V V 3 14 OA IA Isolated DC-DC converters V Logic level shifting 4 13 V OB IB V V 5 12 OC IC V 6 11 V OD ID V 7 10 E1 V E2 GND89 1 GND 2 CAUTION It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. The components featured in this data sheet are not to be used in military or aerospace applications or environments Avago Technologies - 1 -ACCL-9410 Ordering Information Data Sheet Ordering Information Channel Option RoHS Part number Package Surface Mount Tape & Reel Quantity Configuration Compliant ACCL-9410 Quad, -000E Narrow Body X 50 per tube Bi-directional, 3/1 SOIC-16 -500E X X 1000 per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Solder Reflow Profile Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used. Regulatory Information Pending approval by the following organizations: UL Pending UL1577, component recognition program Truth Table Input Output Output Input Output Remark Supply VDD Supply VDD Enable H H H H or Open H Input logic High during normal operation. H L H H or Open L Input logic Low during normal operation. H X H L Z Output is at high impedance state when output Enable is set Low L X H H or Open H When input V is not powered, the output default is logic High. DD X X L X Indeterminate When output V is not powered, the output goes into DD indeterminate state. H - high level. L - Low level, X - insignificant Avago Technologies - 2 -