AEAT-9000-1GSH1 (Basic Option) Ultra-precision 17-Bit Absolute Single Turn Encoder Data Sheet Description Features Avago Technologies AEAT-9000 series are high resolu- 17-bit absolute single turn output (131072 absolute tion single turn optical absolute encoders. The 17-bit positions over 360) AEAT-9000 encoder code disc consists of 13 pairs of dif- 2048 CPR A/B channel incremental digital output ferential absolute tracks and 2 pairs of sinusoidal tracks to Interface output is SSI (2wire SSI / 3wire SSI) with RS485 perform 4 bits interpolation. In addition, the encoder in- line transceiver or single ended option corporates photo detectors for electrical alignment on the radial and tilt. AEAT-9000 also comes with 2 channel incre- On-chip interpolation and code correction compensate mental output with the basic of 2048 counts per rotation. for mounting tolerance Selectable direction for Up/Down position counter The AEAT-9000 is a modular absolute encoder that consists of a read head module and a high-precision code disc Electrical alignment output for tilt and locate (HEDG-9000-H13 & HEDG-9000-H14) which is ordered Built-in monitor track for monitoring of LED light level separately . The modular design allows for better flex - Error output for LED degradation ibility to system designers to easily design-in the encoder feedback system. -40 to 115 C operating temperature Applications NOTE: Avago Technologies encoders are not recommend- Typical applications include: ed for use in safety critical applications, e.g., ABS braking systems, power steering, life support systems and critical Rotary applications up to 17 bits/360 absolute position care medical equipment. Avagos products and software Integration into servo motors are not specifically designed, manufactured or autho - Industrial and maritime valve control rized for sale as parts, components or assemblies for the planning, construction, maintenance or direct operation High precision test and measurement machines of a nuclear facility or for use in medical devices or ap- Industrial and factory automation equipments plications. Customer is solely responsible, and waives all Textile, woodworking & packaging machineries rights to make claims against Avago or its suppliers, for all loss, damage, expense or liability in connection with such Nacelle & blades control in wind turbine use. Please contact sales representative if more clarifica - tion is needed. ESD WARNING: HANDLING PRECAUTIONS SHOULD BE TAKEN TO AVOID STATIC DISCHARGE.Absolute Maximum Ratings Parameter Symbol Min. Max. Units Storage Temperature T -40 85 C S Operating Temperature T -40 115 C A Supply Voltage V -0.3 6 V DD Voltages at all input and output pins Vin & Vout -0.3 V +0.3 V DD Note: Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables Recommended Operating Conditions and Characteristics provide conditions for actual device operation. Recommended Operating Conditions Description Symbol Min. Typical Max. Units Notes Temperature T -40 25 115 C A Supply Voltage V 4.5 5 5.5 V Ripple < 100 mVpp DD Input-H-Level Threshold V 2.0 V V Input-H-Level threshold ih DD Input-L-Level Threshold V 0 0.8 V Input-L-Level threshold il Electrical Characteristics Table (VDD = 4.5 to 5.5 V, TA = -40 to +115 C) Electrical characteristics over recommended operating conditions. Typical values at 25 C Parameters Symbol Conditions Min. Typ. Max. Units Operating Currents Total Current I LED current 10 mA typ 94 mA Total Digital Inputs Pull Up Current I Room Temperature -106 -60 -35 A pu Pull down Current I Room Temperature -108 -56 -31 A pd Digital Outputs Ouput-H-Level V I = 2 mA V - 0.5V V V oh oh DD DD Output-L-Level V I = -2mA 0 0.5 V ol ol SSI Serial Interface SCL Clock Frequency (3wire SSI) f 10 MHz clock SCL clock Frequency (2wire SSI) fclock 1.5 MHz Duty Cycle f T ,LH f = 10 MHz 0.4 0.6 clock clock clock (1) Gray Code Monotony Error fclock = 5 MHz, RPM = 100 1 Error step SPI Serial Interface Min Delay : 500 nS clock cycle Min Delay : clock cycle SPI Clock t clock 100 kHZ NSL Incremental A/B (2048cpr) 1 2 3 13 14 15 16 17 1 SCL Cycle error 5.0 V Nominal -8 +8 Deg MSB MSB-1 MSB-2 LSB+3 LSB+2 LSB+1 LSB MSB MSB-1 DOUTPhase error btw A/B 5.0 V Nominal -15 5 +15 Deg Duty error 5.0 V Nominal -23 4 +28 Deg Note: Code monotony error is dependent on customer installation and the bearing and shaft eccentricity being used. Min Delay : clock cycle Min Delay > 20 S 1 2 3 13 14 15 16 17 1 2 SCL MSB MSB-1 MSB-2 LSB+3 LSB+2 LSB+1 LSB MSB MSB-1 DOUT Figure 1a. 2-wire SSI Timing diagram (for single ended drive) Min Delay : 500 nS clock cycle Min Delay : clock cycle NSL 1 2 3 13 14 15 16 17 1 SCL MSB MSB-1 MSB-2 LSB+3 LSB+2 LSB+1 LSB MSB MSB-1 DOUT Figure 1b. 3-wire SSI Timing diagram (for single ended drive) 2 Min Delay : clock cycle Min Delay > 20 S 1 2 3 13 14 15 16 17 1 2 SCL MSB MSB-1 MSB-2 LSB+3 LSB+2 LSB+1 LSB MSB MSB-1 DOUT