AFBR-5903Z Broadcom

AFBR-5903Z/5903EZ/5903AZ FDDI, Fast Ethernet Transceivers in 2 x 5 Package Style Data Sheet Description Features The AFBR-5903Z family of transceivers from Avago Tech- Multisourced2 x 5pack age style with MT-RJ nologies provide the system designer with products receptacle to implement a range of FDDI and ATM (Asynchronous Single+3.3 V power supply Transfer Mode) designsa tthe 100 Mb/s-125MB dr ate. Wave solder and aqueousw ash processc ompatible The transceivers are all supplied in the new industry Full compliance withthe optical performance standard 2 x 5 DIP style with a MT-RJ fiber connector requirements of the FDDI PMD standard interface. Fullc ompliance with the FDDI LCF-PMDstandar d FDDI PMD, ATM and Fast Ethernet 2 km Backbone Links Full compliance with the optical performance requirements of the ATM100 Mb/s physical layer The AFBR-5903Z is a 1300 nm product with optical per- formance compliant with the FDDI PMD standard. The Full compliancewith the optical performance FDDI PMD standard is ISO/IEC 9314-3: 1990 and ANSI requirements of 100 Base-FX versionof IEEE 802.3u X3.166- 1990. RoHS compliance These transceivers for 2 km multimode fiber backbones Receiver output squelchfunc tion enabled are supplied in the small 2 x 5 MT-RJ package style for Applications those designers who want to avoid the larger MIC/R (Media Interface Connector/Receptacle) defined in the Multimodefiber backbonelinks FDDI PMD standard. Multimodefiber wir ingcloset t odeskt op links Avago Technologies also provides several other FDDI Ordering Information products compliant with the PMD and SM-PMD standards. These products are available with MIC/R, ST , SC and FC The AFBR-5903Z 1300 nmpr oduct is available for pro - connector styles. They are available in the 1 x 9, 1 x 13 and duction orders through the Avago TechnologiesC om - 2 x 11 transceiver and 16 pin transmitter/receiver pack- ponent Field Sales Ocffi es and Authorized Distributors age styles for those designs that require these alternate worldwide . configurations. AFBR-5903Z = 0C to +70C The AFBR-5903Z is also useful for both ATM 100 Mb/s No Shield interfaces and Fast Ethernet 100 Base-FX interfaces. The AFBR-5903EZ = 0Ct o +70C ATM Forum User-Network Interface (UNI) Standard, Version Extended Shield 3.0, defines the Physical Layer for 100 Mb/s Multimode AFBR-5903AZ = -40Ct o +85C Fiber Interface for ATM in Section 2.3 to be the FDDI PMD No Shield. Standard. Likewise, the Fast Ethernet Alliance defines the Physical Layer for 100 Base-FX for Fast Ethernet to be the FDDI PMD Standard. Contacty ourA vago Technologies sales representa - ATM applications for physical layers other than 100 tive forinf or mationon these alternative FDDI and ATM Mb/s Multimode Fiber Interface are supported by products. Avago Technologies. Products are available for both the single-mode and the multimode fiber SONET OC-3c (STS-3c), SDH (STM-1) ATM interfaces and the 155 Mb/s- 194 MBd multimode fiber ATM interface as specified in the ATM ForumUNI. Transmitter Sections Package The transmitter section of the AFBR-5903Z utilizes a 1300 The overall package concept for the Avago Technologies nm Surface Emitting InGaAsP LED. This LED is packaged transceiver consists of the following basic elements two in the optical subassembly portion of the transmitter optical subassemblies, an electrical subassembly and the section. It is driven by a custom silicon IC which converts housing as illustrated in Figure 1. differential PECL logic signals, ECL referenced (shifted) to The package outline drawing and pin out are shown in Figures a +3.3 V supply, into an analog LED drive current. 2 and 3. The details of this package outline and pin out are compliant with the multisource denfi ition of the 2 x 5 DIP. Receiver Sections The low prolfi e of the Avago Technologies transceiver design The receiver section of the AFBR-5903Z utilizes an InGaAs complies with the maximum height allowed for the MT-RJ PIN photodiode coupled to a custom silicon transimped- connector over the entire length of the package. ance preamplifier IC. It is packaged in the optical sub- The optical subassemblies utilize a high-volume assembly assemblypor tion of the receiver. process together with low-cost lens elements which result This PIN/preamplifier combination is coupled to a custom in a cost-eeff ctive building block. quantizer IC which provides the final pulse shaping for The electrical subassembly consists of a high volume mul- the logic output and the Signal Detect function. The Data tilayer printed circuit board on which the IC and various output is diff erential. The Signal Detect output is single- surface-mounted passive circuit elements are attached. ended. Both Data and Signal Detect outputs are PECL The receiver section includes an internal shield for the elec- compatible, ECL referenced (shifted) to a +3.3 V power trical and optical subassemblies to ensure high immunity to supply. The receiver outputs, Data Out and Data Out Bar, external EMI efi lds. are squelched at Signal Detect Deassert. That is, when the light input power decreases to a typical -38 dBm or less, The outer housing is electrically conductive and is at receiver the Signal Detect Deasserts, i.e. the Signal Detect output signal ground potential. The MT-RJ port is molded of filled goes to a PECL low state. This forces the receiver outputs, nonconductive plastic to provide mechanical strength Data Out and Data Out Bar to go to steady PECL levels and electrical isolation. The solder posts of the Avago High and Low respectively. Technologies design are isolated from the internal circuit of the transceiver. The transceiver is attached to a printed circuit board with the ten signal pins and the two solder posts which exit the bottom of the housing. The two solder posts provide the primary mechanical strength to withstand the loads imposed on the transceiver by mating with the MT-RJ connectored fiber cables. RX SUPPLY DATA OUT QUANTIZER IC PIN PHOTODIODE DATA OUT PRE-AMPLIFIER SUBASSEMBLY SIGNAL R X GROUND MT-RJ DETECT RECEPTACLE TX GROUND DATA IN LED OPTICAL SUBASSEMBLY LED DRIVER IC DATA IN TX SUPPLY Figure 1. Block Diagram. 2