Backplane BCM8020 EIGHT-CHANNEL MULTIRATE 1.03.2-GBPS TRANSCEIVER FEATURES SUMMARY OF BENEFITS Eight independent transceivers supporting multiple data rates One device supports a variety of applications including Gigabit Ethernet, 1x and 2x Fibre Channel, OC-48 SONET (with/without from 1.0 Gbps to 3.2 Gbps including 1.06 Gbps, 1.25 Gbps, FEC), InfiniBand , 10-Gigabit Ethernet, 10-Gigabit Fibre 2.12 Gbps, 2.488 Gbps, 2.5 Gbps, 2.667 Gbps, 3.125 Gbps, and Channel, or others. 3.1875 Gbps Flexible architecture supports programmable configurations Multiconfigurable to support various operating modes enabling an aggregate data transfer rate of over 20 Mbps. Built- Eight independent 1.0- to 3.2-Gbps SerDes channels in redundancy mode provides high availability to support critical Dual quad 1.0- to 3.2-Gbps SerDes with channel alignment line-side or backplane applications. The high-speed to high-speed SerDes-to-SerDes retimer mode: CML and XAUI interfaces retimer mode extends the use of longer traces on line-card Full mesh switching maps any XAUI port to any XGMII port designs. for full redundancy on both transmitter and receiver Advanced 0.13 CMOS process technology provides Selectable TBI DDR/RTBI or XGMII parallel interface unparalleled performance while achieving the lowest possible HSTL (1.8V or 1.5V) and SSTL 2 parallel interface power consumption Low power dissipation Eases line-card designs allowing for multiple connectors or low- Less than 300 mW per transceiver channel including I/O cost PCB materials such as FR4 High-performance programmable receive equalization and Drive PMD devices or backplane directly with no external transmit pre-emphasis cleanup circuit required Transmit pre-emphasis for interoperability with CML SerDes Simplifies manufacturability with integrated built-in self-test Receive equalization for copper interconnects (BIST), high-speed and low-speed loopbacks, and programmable PRBS generator/checker Enhanced test capability Serial and parallel loopback, BIST, 10G BERT, and random Decreases complexity and reduces board space on multichannel Ethernet packet generation line-card designs IEEE (1149.1) JTAG APPLICATIONS Compact 23-mm 23-mm package with no external components required No requirement for heat sink or airflow 1-Gigabit Ethernet and 10-Gigabit Ethernet LAN, MAN, WAN switches and routers 1x, 2x, or 10-Gbps Fibre Channel, InfiniBand, SONET network cards Advanced test equipment (ATE) Two Independent Quad SerDes Application Diagram TX RX BCM8702 2x XENPAK ASIC/MAC BCM8020 BCM8020 TX 2x XAUI 2x XGMII/TBI 2x XGMII/TBI 2x XAUI RX BCM8702OVERVIEW 10G XAUI 0 10G XGMII 0 Channel 0 (13.2G) Channel 0 (TBI, RTBI) Channel 1 (13.2G) Channel 1 (TBI, RTBI) Channel 2 (13.2G) Channel 2 (TBI, RTBI) Channel 3 (13.2G) Channel 3 (TBI, RTBI) (Control/Clocking) Bus MUX 10G XAUI 1 10G XGMII 1 Channel 4 (13.2G) Channel 4 (TBI, RTBI) Channel 5 (13.2G) Channel 5 (TBI, RTBI) Channel 6 (13.2G) Channel 6 (TBI, RTBI) Channel 7 (13.2G) Channel 7 (TBI, RTBI) (Control/Clocking) MGMT PBERT MDIO/MDC Required: 1.2V, 2.5V, BCM8020 I/O options: 1.5V, 1.8V, 2.5V, or 3.3V BCM8020 Block Diagram The BCM8020 device integrates eight independent serializer/ On the serial side of the device, transmitters and receivers support serial deserializer (SerDes) channels leveraging Broadcoms high- transmissions rates ranging from 1 Gbps to 3.2 Gbps. An on-chip phase performance mixed-signal design experience along with advanced 0.13 lock loop (PLL) synthesizes the supplied reference clock to support the CMOS process technology. This, combined with a robust architecture desired transmit rate, while clock and data recovery (CDR) units recover offering the highest degree of flexibility, results in a highly the receive rate clock for timing. The interface can support single- programmable, lowest power SerDes solution for network line-card and channel (octal) or dual-channel quad (XAUI) differential CML I/O. backplane applications. For high-speed serial copper connections, the device incorporates both An internal switch connects the parallel and serial ports to enable fully transmit pre-emphasis on the transmit channels and receive equalization redundant operation. The switch enables an active serial link to be on the receive channels. Transmit pre-emphasis is programmable to switched to the parallel interface, while a protection serial link can be improve the overall cable reach and compensate for electrical continuously monitored to ensure its condition. If the active link fails, the imperfections associated with traces and connectors. Receive protection link can be instantly switched through external control to the equalization provides optimal performance over a variety of receive parallel interface. interfaces. On the parallel side of the device, transmitters and receivers interface Highly programmable test capabilities exist within the device to support with either 5-bit (RTBI) or 10-bit (TBI) wide data on each channel or can high-speed and low-speed loopback using generators/checkers that be configured to interface to 32-bit wide data (XGMII) along with the support PRBS 27 to 231 patterns along with IEEE 802.3ae-defined clock and control signals. The low-speed I/O supports HSTL (1.5V or test patterns. A complete evaluation kit, including an evaluation board, 1.8V) or SSTL 2 (2.5V) interfaces. related software, and documentation is available upon request. Broadcom , the pulse logo, Connecting everything , and the Connecting everything logo are among the trademarks of Broadcom Corporation and/or its affiliates in the United States, certain other countries and/or the EU. Any other trademarks or trade names mentioned are the property of their respective owners. BROADCOM CORPORATION Phone: 949-450-8700 16215 Alton Parkway, P.O. Box 57013 Fax: 949-450-8710 Irvine, California 92619-7013 E-mail: info broadcom.com Web: www.broadcom.com 2006 by BROADCOM CORPORATION. All rights reserved. 8020-PB05-R 04/14/06