Pin16 Pin5 Pin15 Pin6 Pin14 Pin7 Pin13 Pin8 Q2 Q1 MGA-13516 High Gain, High Linearity, Active Bias, Low Noise Amplifier Data Sheet Description Features Avago Technologies MGA-13516 is a two stage, easy-to- Lownoise figur e use GaAs MMIC Low Noise Amplifier (LNA) with active bias . Highgain The LNA has low noise with good input return loss and Good IRL high linearity achieved through the use of Avago Tech- nologies proprietary 0.5um and 0.25um GaAs Enhance- Highlinear ityper formance ment-mode pHEMT process. Both LNAs inside have extra Highr everseisola tion feature that allows a designer to adjust supply current. Externally adjustable supply current The first stage has an additional feature where the gain can be adjusted externally without affecting noise figure . Externally adjustable gain Minimum matching needed for input, output and the 1 GaAs E-pHEMT Technology inter-stage betweenthe twoLNA. Low cost QFNpack age It is designed for optimum use between 400MHz to Excellentunif ormity inpr oduct specifications 1.5GHz. For optimum performance at higher frequency from 1.4GHz to 2.7GHz, the MGA-14516 is recommended. Specifications Both MGA-13516 & MGA-14516 share the same package 900MHz Q1 :5V ,45mA (typ)Q2 :5V ,110mA andpinout . 31.8dB G ain Pin Configuration and Package Marking 0.66dB Noise F igure 3 4.0 x4.0 x 0.85 mm 16-lead QFN 13 dBIRL 38 dBm Output IP3 23.5 dBm Output Power at1dB gain c ompression Pin12 Pin1 13516 Applications Pin11 Pin2 YYWW Pin10 Pin3 Low noise amplifier for cellular infrastructure including XXXX Pin9 Pin4 GSM, CDMA and W-CDMA. Otherv ery low noise applications. Note: TOPVIEW BOTTOMVIEW 1. Enhancement mode technology employs positive Vgs, thereby eliminating the need of negative gate voltage associated with conventional depletionmode devic es. Pin Description Pin Description 1 Not Used 9 NotU sed 1 12 2 NC 10 RFout Attention: Observe precautions for 2 11 3 RFin 11 RFout handling electrostatic sensitive devices 4 RFgnd1 12 Not Used 3 10 ESD Machine Model = 40 V 5 Vbias1 13 Vg ESD Human Body Model = 200 V 4 9 6 FB1 14 RFgnd2 Refer to Avago Application Note A004R: 7 RFout1 15 Vm Electrostatic Discharge, Damage and Control. 8 RFin2 16 Vbias Notes: Package marking provides orientation and identification13516 is the Product Identification, YYWW is the Date Code, XXXX is the last 4 digits of thelot number . 5 16 6 15 7 14 8 13 1 MGA-13516 Absolute Maximum Rating Symbol Parameter Units Absolute Max. Vdd1 DeviceSupply Voltage V 5.5 Vbias1 Control Voltage V 3.5 Vdd2 Device Voltage, RFoutput to ground V 5.5 Vbias Control Voltage V 5.5 Idd2 Device Drain Current mA 150 P CW RF InputP ower (Vdd1 = 5.0V,Idd1=45mA ) dBm 20 in,max 3 P Total Power Dissipation W 1.30 diss T Junction Temperature C 150 j T Storage Temperature C -65t o 150 STG 1-3 o Thermal Resistance (V =V =V =5V), = 36 C/W dd1 dd2 bias jc Notes: 1. Operation of this device in excess of anyof these limits may cause permanent damage. 2. Thermal resistance measured using Infra-Red Microscopy Technique. o o o 3. Board temperature T is25 C. Derate 28mW/ Cf or T >120 C. B B 4 Product Consistency Distribution Charts T = 25C, 900MHz, Vdd1=5V, Vdd2=5V, Vbias=5V, F =900MHz, unless statedother wise. A RF LSL USL LSL USL CPK=3.22 CPK=3.26 36 38 40 52 70 80 90 100 110 120 130 140 150 42 44 46 48 50 54 Figure 1. Idd1 distribution LSL=37mA , USL=53mA Figure 2. Idd2 distribution LSL=75mA , USL=140mA USL LSL USL CPK=4.40 CPK=2.09 30.0 30.5 31.0 31.5 32.0 32.5 33.0 33.5 34.0 .5 .6 .7 .8 .9 1 1.1 1.2 Figure 3. Gain distribution LSL=30.2dB , USL=33.8dB NF distribution USL=1dB Notes:: 4. Distribution data sample size is 500 samples taken from 3 different wafer lots. Future wafer allocated to this product may have nominal values anywhere between the upper andlo wer limits. Circuit losses have not been de-embedded fromac tualmeasur ements. 2