Pin 16 Pin 5 Pin 15 Pin 6 Pin 14 Pin 7 Pin 13 Pin 8 Q2 Q1 MGA-14516 High Gain, High Linearity Active Bias Low Noise Amplier Data Sheet Description Features Avago Technologies MGA-14516 is a two stage, easy-to- Low noise gure use GaAs MMIC Low Noise Amplier (LNA) with active High gain bias. The LNA has low noise with good input return loss Good IRL and high linearity achieved through the use of Avago Technologies proprietary 0.5um and 0.25um GaAs En- High linearity performance hancement-mode pHEMT process. Both LNAs have an High reverse isolation extra feature inside that allows a designer to adjust supply Externally adjustable supply current current. The rst stage has an additional feature where the gain can be adjusted externally without aecting noise Externally adjustable gain gure. Minimum matching needed for input, output and 1 GaAs E-pHEMT Technology the inter-stage between the two LNA. Low cost QFN package It is designed for optimum use between 1.4GHz to 2.7GHz. Excellent uniformity in product specications For optimum performance at lower frequency from 400MHz to 1.5GHz, the MGA-13516 is recommended. Specications Both MGA-13516 & MGA-14516 share the same package 1.95GHz Q1 : 5V, 45mA (typ) Q2 : 5V, 110mA and pinout. 31.7 dB Gain Pin Conguration and Package Marking 0.68 dB Noise Figure 3 4.0 x 4.0 x 0.85 mm 16-lead QFN 13 dB IRL 38 dBm Output IP3 23.5 dBm Output Power at 1dB gain compression Pin 12 Pin 1 14516 Applications Pin 11 Pin 2 YYWW Pin 10 Pin 3 Low noise amplier for cellular infrastructure including XXXX Pin 9 Pin 4 GSM, CDMA, W-CDMA, TD-SCDMA and WiMAX. Other very low noise applications. Note: TOP VIEW BOTTOM VIEW 1. Enhancement mode technology employs positive Vgs, thereby eliminating the need of negative gate voltage associated with conventional depletion mode devices. Pin Description Pin Description 1 Not Used 9 Not Used 1 12 2 NC 10 RFout Attention: Observe precautions for 2 11 3 RFin 11 RFout handling electrostatic sensitive devices. 4 RFgnd1 12 Not Used 3 10 ESD Machine Model = 40 V 5 Vbias1 13 Vg ESD Human Body Model = 200 V 4 9 6 FB1 14 RFgnd2 Refer to Avago Application Note A004R: 7 RFout1 15 Vm Electrostatic Discharge, Damage and Control. 8 RFin2 16 Vbias Notes: Package marking provides orientation and identication 14516 is the Product Identication, YYWW is the Date Code, XXXX is the last 4 digits of the lot number. 5 16 6 15 7 14 8 13 1 Absolute Maximum Rating Symbol Parameter Units Absolute Max. Vdd1 Device Supply Voltage V 5.5 Vbias1 Control Voltage V 3.5 Vdd2 Device Voltage, RF output to ground V 5.5 Vbias Control Voltage V 5.5 Idd2 Device Drain Current mA 150 P CW RF Input Power (Vdd1 = 5.0V, Idd1=45mA) dBm 20 in,max 3 P Total Power Dissipation W 1.30 diss T Junction Temperature C 150 j T Storage Temperature C -65 to 150 STG 1-3 o Thermal Resistance (V =V =V =5V), = 36 C/W dd1 dd2 bias jc Notes: 1. Operation of this device in excess of any of these limits may cause permanent damage. 2. Thermal resistance measured using Infra-Red Microscopy Technique. o o o 3. Board temperature T is 25 C. Derate 28mW/ C for T >120 C. B B 4 Product Consistency Distribution Charts T = 25 C, 1.95GHz, Vdd1=5V, Vdd2=5V, Vbias=5V, F =1.95GHz, unless stated otherwise. A RF USL LSL USL LSL CPK = 2.67 CPK = 3.08 34 36 38 40 42 44 46 48 50 52 54 70 80 90 100 110 120 130 140 150 Figure 1. Idd1 distribution LSL = 35mA, USL = 52mA Figure 2. Idd2 distribution LSL = 75mA, USL = 140mA USL USL LSL CPK = 3.00 CPK = 3.72 30.0 30.5 31.0 31.5 32.0 32.5 33.0 33.5 .60 .65 .70 .75 .80 .85 .90 .95 1.00 Figure 3. Gain distribution LSL = 30.2dB, USL = 33.3dB Figure 4. NF distribution USL = 1dB Notes: 4. Distribution data sample size is 500 samples taken from 3 dierent wafer lots. Future wafer allocated to this product may have nominal values anywhere between the upper and lower limits. Circuit losses have not been de-embedded from actual measurements. 2