MGA-30689 40MHz - 3000MHz Flat Gain High Linearity Gain Block Data Sheet Description Features Avago Technologies MGA-30689 is a flat gain, high Flat Gain 14dB +/-0.5dB, 40MHz to 2600MHz linearity, low noise, 22dBm Gain Block with good OIP3 High linearity achieved through the use of Avago Technologies propri- Built in temperature compensated internal bias circuitry etary 0.25um GaAs Enhancement-mode pHEMT process. No RF matching components required The device required simple dc biasing components to 1 GaAs E-pHEMT Technology achieve wide bandwidth performance. The tempera- Standard SOT89 package ture compensated internal bias circuit provides stable Single, Fixed 5V supply current over temperature and process threshold voltage Excellent uniformity in product specifications variation. MSL-2 and Lead-free halogen free The MGA-30689 is housed inside a standard SOT89 High MTTF for base station application package (4.5 x 4.1 x 1.5 mm). Specifications Applications 900MHz 5V, 104mA (typical) IF amplifier, RF driver amplifier 14.3 dB Gain General purpose gain block 43 dBm Output IP3 3.0 dB Noise Figure Component Image 22.3 dBm Output Power at 1dB gain compression 1950MHz, 5V, 104mA (typical) 14.6 dB Gain 40 dBm Output IP3 6GX 3.3 dB Noise Figure 22.5 dBm Output Power at 1dB gain compression 1 2 3 3 2 1 Note: RFin GND RFout RFout GND RFin 1. Enhancement mode technology employs positive gate voltage, thereby eliminating the need of negative gate voltage associated Top View Bottom View with conventional depletion mode devices. Notes: Package marking provides orientation and identification Attention: Observe precautions for 6G = Device Code X = Month of manufacture handling electrostatic sensitive devices. ESD Machine Model = 75 V ESD Human Body Model = 450 V Refer to Avago Application Note A004R: Electrostatic Discharge, Damage and Control. 2 Absolute Maximum Rating T =25C A 3 Symbol Parameter Units Absolute Max. Thermal Resistance = 53.5C/W jc (Vdd = 5V, Ids = 100mA, Tc = 85C) V Device Voltage, RF output to ground V 5.5 dd,max Notes: P CW RF Input Power dBm 20 in,max 2. Operation of this device in excess 4 of any of these limits may cause P Total Power Dissipation W 0.75 diss permanent damage. T Junction Temperature C 150 j, max 3. Thermal resistance measured using Infrared measurement technique. T Storage Temperature C -65 to 150 STG 4. This is limited by maximum Vdd and Ids. Derate 18.7 mW/C for Tc>110C. 5, 6 Product Consistency Distribution Charts LSL USL LSL USL 80 90 100 110 120 13.5 14 14.5 15 15.5 16 16.5 Figure 1. Ids, LSL=80mA , nominal=104mA, USL=125mA Figure 2. Gain, LSL=13.7dB, nominal=14.6dB, USL=16.7dB LSL LSL 37 38 39 40 41 42 43 44 45 21.2 21.6 22 22.4 22.8 23.2 Figure 3. OIP3, LSL=37.5dBm, nominal=41.5dBm Figure 4. P1dB, LSL=21.2dBm, nominal=22.5dBm Notes: USL 5. Distribution data sample size is 500 samples taken from 3 different wafer lots and 6 different wafers. Future wafers allocated to this product may have nominal values anywhere between the upper and lower limits. 6. Measurements were made on a characterization test board, which represents a trade-off between optimal OIP3, gain and P1dB. Circuit trace losses have not been de-embedded from measurements above. 2.8 3 3.2 3.4 3.6 3.8 4 Figure 5. NF, nominal=3.23dB, USL=4dB 2