MGA-30789 2 - 6GHz High Linearity Gain Block Data Sheet Description Features Avago Technologies MGA-30789 is a broadband, high High linearity linearity gain block MMIC amplifier achieved through Built in temperature compensated internal bias the use of Avago Technologies proprietary 0.25um GaAs circuitry Enhancement-mode pHEMT process. No RF matching components required The device required simple dc biasing components to 1 GaAs E-pHEMT Technology achieve wide bandwidth performance. The temperature Standard SOT89 package compensated internal bias circuit provides stable current over temperature and process threshold voltage Single, Fixed 5V supply variation. Excellent uniformity in product specifications The MGA-30789 is housed inside a low cost RoHS MSL-2 and Lead-free halogen free compliant SOT89 industry standard SMT package (4.5 x High MTTF for base station application 4.1 x 1.5 mm). Specifications Component Image 3.5GHz 5V, 100mA (typical) 11.7 dB Gain 41.8 dBm Output IP3 7GX 3.3 dB Noise Figure 25 dBm Output Power at 1dB gain compression 3 2 1 1 2 3 5GHz 5V, 100mA (typical) RFin GND RFout RFout GND RFin 8.8 dB Gain Top View Bottom View 40 dBm Output IP3 Notes: 2.7 dB Noise Figure Package marking provides orientation and identification 7G = Device Code 25.7 dBm Output Power at 1dB gain compression X = Month of Manufacture Applications Attention: Observe precautions for RF driver amplifier handling electrostatic sensitive devices. General purpose gain block ESD Machine Model = 110 V Note: ESD Human Body Model = 2000 V 1. Enhancement mode technology employs positive gate voltage, Refer to Avago Application Note A004R: thereby eliminating the need of negative gate voltage associated Electrostatic Discharge, Damage and Control. with conventional depletion mode devices. 1 Absolute Maximum Rating T =25C Thermal Resistance A 3 Symbol Parameter Units Absolute Max. Thermal Resistance = 52C/W JC (Vdd = 5, Ids = 88 mA, Tc = 85C) V Device Voltage, RF output to ground V 5.5 dd,max Notes: P CW RF Input Power dBm 24 in,max 1. Operation of this device in excess of any of 3 P Total Power Dissipation W 0.75 diss these limits may cause permanent damage. 2. Thermal resistance measured using Infrared T Junction Temperature C 150 j,MAX measurement technique. T Storage Temperature C -65 to 150 STG 3. This is limited by maximum Vdd and Ids. Derate 19.2 mW/C for Tc >111C. 1, 2 Product Consistency Distribution Charts LSL USL LSL USL 90 100 110 8 8.5 9 9.5 10 Figure 1. Ids, LSL=83mA , nominal=100mA, USL=117mA Figure 2. Gain, LSL=8dB, nominal=8.8dB, USL=10.3dB LSL LSL 38 39 40 41 42 24.5 25 25.5 26 Figure 3. OIP3, LSL=38dBm, nominal=41dBm Figure 4. P1dB, LSL=24.5dBm, nominal=25.7dBm USL Notes: 1. Distribution data sample size is 2000 samples taken from 3 different wafer lots. Future wafers allocated to this product may have nominal values anywhere between the upper and lower limits. 2. Measurements were made on a characterization test board, which represents a trade-off between optimal OIP3, gain and P1dB. Circuit trace losses have not been de-embedded from measurements above. 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 Figure 5. NF, nominal=2.7dB, USL=3.3dB 2