MGA-30889 40MHz - 2600MHz Flat Gain High Linearity Gain Block Data Sheet Description Features Avago Technologies MGA-30889 is a broadband, flat gain, Flat Gain 15dB +/-0.25dB, 40MHz to 2600MHz high linearity gain block MMIC amplifier achieved through High linearity the use of Avago Technologies proprietary 0.25um GaAs Built in temperature compensated internal bias circuitry Enhancement-mode pHEMT process. No RF matching components required The device required simple dc biasing components to 1 GaAs E-pHEMT Technology achieve wide bandwidth performance. The temperature compensated internal bias circuit provides stable current Standard SOT89 package over temperature and process threshold voltage Single, Fixed 5V supply variation. Excellent uniformity in product specifications The MGA-30889 is housed inside a low cost RoHS MSL-2 and Lead-free halogen free compliant SOT89 industry standard SMT package (4.5 x 4.1 x 1.5 mm). High MTTF for base station application Component Image Specifications 900MHz 5V, 65mA (typical) 15.5 dB Gain 38 dBm Output IP3 8GX 1.9 dB Noise Figure 20 dBm Output Power at 1dB gain compression 3 2 1 1 2 3 1950MHz, 5V, 65mA (typical) RFin GND RFout RFout GND RFin 15.7 dB Gain Top View Bottom View 36 dBm Output IP3 Notes: 2 dB Noise Figure Package marking provides orientation and identification 8G = Device Code 20.3 dBm Output Power at 1dB gain compression X = Month of Manufacture Applications Attention: Observe precautions for IF amplifier, RF driver amplifier handling electrostatic sensitive devices. General purpose gain block ESD Machine Model = 50 V ESD Human Body Model = 400 V Note: 1. Enhancement mode technology employs positive gate voltage, Refer to Avago Application Note A004R: thereby eliminating the need of negative gate voltage associated Electrostatic Discharge, Damage and Control. with conventional depletion mode devices. 1 Absolute Maximum Rating T =25C Thermal Resistance A 2 Symbol Parameter Units Absolute Max. Thermal Resistance = 76C/W JC (Vdd = 5 V, Ids = 57.5 mA, Tc = 85C) V Device Voltage, RF output to ground V 5.5 dd,max Notes: P CW RF Input Power dBm 20 in,max 1. Operation of this device in excess of any of 3 P Total Power Dissipation W 0.47 diss these limits may cause permanent damage. 2. Thermal resistance measured using Infrared T Junction Temperature C 150 j,MAX measurement technique. T Storage Temperature C -65 to 150 STG 3. This is limited by maximum Vdd and Ids. Derate 13.2 mW/C for Tc >114C. 1, 2 Product Consistency Distribution Charts LSL USL LSL USL 60 70 14.5 15 15.5 16 16.5 Figure 1. Ids, LSL=53mA , nominal=65mA, USL=77mA Figure 2. Gain, LSL=14.6dB, nominal=15.7dB, USL=16.8dB LSL LSL 33 34 35 36 37 38 39 19.2 19.6 20 20.4 20.8 Figure 3. OIP3, LSL=33dBm, nominal=36dBm Figure 4. P1dB, LSL=19.2dBm, nominal=20.3dBm USL Notes: 1. Distribution data sample size is 3000 samples taken from 3 different wafer lots. Future wafers allocated to this product may have nominal values anywhere between the upper and lower limits. 2. Measurements were made on a characterization test board, which represents a trade-off between optimal OIP3, gain and P1dB. Circuit trace losses have not been de-embedded from measurements above. 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 Figure 5. NF, nominal=2dB, USL=2.7dB 2