MGA-30989 2 - 6GHz, High Linearity Gain Block Data Sheet Description Features Avago Technologies MGA-30989 is a broadband, high High linearity linearity gain block MMIC amplifier achieved through Built in temperature compensated internal bias circuitry the use of Avago Technologies proprietary 0.25um GaAs No RF matching components required Enhancement-mode pHEMT process. 1 GaAs E-pHEMT Technology The device required simple dc biasing components to Standard SOT89 package achieve wide bandwidth performance. The temperature compensated internal bias circuit provides stable current Single, Fixed 5V supply over temperature and process threshold voltage variation. Excellent uniformity in product specifications The MGA-30989 is housed inside a low cost RoHS MSL-1 and Lead-free halogen free compliant SOT89 industry standard SMT package (4.5 x High MTTF for base station application 4.1 x 1.5 mm). Specifications Component Image 3.5GHz, 5V, 51mA (typical) 12 dB Gain 36.8 dBm Output IP3 9GX 2 dB Noise Figure 23.6 dBm Output Power at 1dB gain compression 3 2 1 1 2 3 5GHz, 5V, 51mA (typical) RFin GND RFout RFout GND RFin 9.6 dB Gain Top View Bottom View 38.4 dBm Output IP3 1.65 dB Noise Figure Notes: Package marking provides orientation and identification 23.8 dBm Output Power at 1dB gain compression 9G = Device Code X = Month of Manufacture Applications IF amplifier, RF driver amplifier Attention: Observe precautions for General purpose gain block handling electrostatic sensitive devices. ESD Machine Model = 50 V Note: 1. Enhancement mode technology employs positive gate voltage, ESD Human Body Model = 1000 V thereby eliminating the need of negative gate voltage associated Refer to Avago Application Note A004R: with conventional depletion mode devices. Electrostatic Discharge, Damage and Control. 1 Absolute Maximum Rating T =25C Thermal Resistance A 2 Symbol Parameter Units Absolute Max. Thermal Resistance = 81.2C/W JC (Vdd = 5 V, Ids = 48 mA, Tc = 85C) V Device Voltage, RF output to ground V 5.5 dd,max Notes: P CW RF Input Power dBm 24 in,max 1. Operation of this device in excess of any of 3 P Total Power Dissipation W 0.47 diss these limits may cause permanent damage. 2. Thermal resistance measured using Infrared T Junction Temperature C 150 j,MAX measurement technique. T Storage Temperature C -65 to 150 STG 3. This is limited by maximum Vdd and Ids. Derate 12.3 mW/C for Tc >112C. 1, 2 Product Consistency Distribution Charts LSL USL LSL USL 50 60 8.5 9 9.5 10 10.5 Figure 1. Ids, LSL=42mA , nominal=51mA, USL=66mA Figure 2. Gain, LSL=8.5dB, nominal=9.6dB, USL=10.5dB LSL LSL 35 36 37 38 39 22 22.5 23 23.5 24 24.5 Figure 3. OIP3, LSL=35dBm, nominal=38.4dBm Figure 4. P1dB, LSL=22dBm, nominal=23.8dBm USL Notes: 1. Distribution data sample size is 3000 samples taken from 3 different wafer lots. Future wafers allocated to this product may have nominal values anywhere between the upper and lower limits. 2. Measurements were made on a characterization test board, which represents a trade-off between optimal OIP3, gain and P1dB. Circuit trace losses have not been de-embedded from measurements above. 1.4 1.5 1.6 1.7 1.8 1.9 2 2.1 Figure 5. NF, nominal=1.65dB, USL=2.1dB 2