MGA-43828 925960 MHz Linear Power Amplifier Module Data Sheet Description Features 1 High linearity performance : Max -50 dBc ACLR1 at 27 The Avago MGA-43828 is a fully matched, highly linear dBm linear output power (biased with 5.0 V supply) power amplifier (PA) designed for use in the 925-960 MHz band. Based on Avagos proprietary 0.25 m GaAs High gain: 33 dB E-pHEMT technology, the device features high linearity, Good efficiency gain and power-added efficiency (PAE) with integrated Fully matched power detector and shutdown functions. The MGA-43828 Built-in detector is ideal for use as a final stage PA for Small Cell base trans - ceiver station (BTS) applications. 2 GaAs E-pHEMT Technology Low cost small package size: (5.0 5.0 0.9) mm Component Image MSL3 (5.0 5.0 0.9) mm Package Outline Lead free/Halogen free/RoHS compliance Specifications A 940 MHz 5.0 V, Idqtotal =316 mA (typ), W-CDMA Test VAGO Notes: model 1, 64DPCH downlink signal 43828 Package marking provides orientation and identification YYWW PAE: 14.7% 43828 = Device part number XXXX 1 YYWW = Year and work week 27 dBm linear P ACLR1 = -50 dBc out XXXX = Assembly lot number 33 dB Gain TOP VIEW Detector range: 20 dB Pin Configuration Applications Final stage high linearity amplifier for Picocell and Enterprise Femtocell PA targeted for small cell BTS downlink applications. Notes: 1. W-CDMA Test model 1, 64DPCH downlink signal 21 Gnd Gnd 1 2. Enhancement mode technology employs positive V , thereby GS 20 Gnd Gnd 2 eliminating the need of negative gate voltage associated with 19 RFout conventional depletion mode devices. NC 3 18 RFout RFin 4 Functional Block Diagram 17 RFout NC 5 Vdd2 Vdd3 16 Gnd Gnd 6 (5.0 x 5.0 x 0.9) mm 15 Gnd NC 7 nd rd 2 Stage 3 Stage RFin RFout Biasing Circuit Attention: Observe Precautions for Vc2 Vc3 VddBias Vdet handling electrostatic sensitive devices. ESD Machine Model = 60 V ESD Human Body Model = 400 V Refer to Avago Application Note A004R: Electrostatic Discharge Damage and Control. 28 NC NC 8 27 Gnd Vc2 9 26 Vdd2 Vc3 10 25 Gnd Gnd 11 24 Vdd3 VddBias 12 23 Vdd3 Gnd 13 22 Vdd3 Vdet 14 1 2,3 Absolute Maximum Rating T =25 C Thermal Resistance A q = 12 C/W jc Symbol Parameter Units Absolute Max. Notes: V , V Supply voltages, bias supply voltage V 6.0 1. Operation of this device in excess of any of dd ddBias these limits may cause permanent damage. V Control Voltage V (V ) c dd 2. Thermal resistance measured using Infra- Red Measurement Technique. P CW RF Input Power dBm 20 in,max 3. Board temperature (T ) is 25 C , for T >91 B B 3 P Total Power Dissipation W 4.9 diss C derate the device power at 83 mW per C rise in Board (package belly) temperature. T Junction Temperature C 150 j T Storage Temperature C -65 to 150 STG Electrical Specifications T = 25 C, Vdd = VddBias = 5.0 V, Vc2=3.5 V, Vc3=2.8 V, Idqtotal = 316 mA, RF performance at 940 MHz, W-CDMA Test A model 1, 64DPCH downlink signal operation, unless otherwise stated. Symbol Parameter and Test Condition Units Min. Typ. Max. Vdd Supply Voltage V - 5.0 - Idqtotal Quiescent Supply Current mA - 316 560 Gain Gain dB 31 33 - OP1dB Output Power at 1dB Gain Compression dBm - 36 - ACLR1 P =27.0 dBm W-CDMA Test model 1, 64DPCH downlink signal dBc - -50 - out PAE Power Added Efficiency % 13 14.7 - S11 dB - 13.9 - Input Return Loss, 50 source DetR Detector RF dynamic range dB - 20 - 2fo 2fo Harmonics dBc -35 (W-CDMA Test model 1, 64DPCH downlink signal) 2