MGA-665P8 GaAs Enhancement-Mode PHEMT 0.5 6 GHz Low Noise Amplifier Data Sheet Description Features Avagos MGA-665P8 is an economical, easy-to-use SurfaceM ount,2.0 x2.0 x 0.75 mm 8-lead LPCC GaAs MMIC Low Noise Amplifier (LNA) with a unique Active-lowpo wer-down function active-low power-down function. The LNA has low Single+3 Vsupply oper ation noise figure and high gain achieved through the use of Avago Technologies proprietary GaAs Enhancement- Lownoise andhigh gain MMIC mode PHEMT process. It is housed in a miniature 2.0 x Output 50 ma tch 2.0 x 0.75 mm 8-pin Leadless-Plastic-Chip-Carrier (LPCC) Excellentisola tion package. The compact footprint and low profile coupled with low noise, high gain and high linearity makes the Minimal matchand e xternalbiasing c omponents MGA-665P8 an ideal choice as an LNA for broadband Housed inminia ture 2x 2 x 0.75 mm LPCC package general-purpose applications. Its excellent broadband Pb-free& MSL -1pack age isolationalso makes it agood buff eramplifier . Specifications The output of the MGA-665P8 provides a very good broadband match to 50 . Its input requires a simple 0.5t o 6 GHz operation external LC network to provide a low noise figure and At 3 V, 20.5 mA, 2.4 GHz: good input return loss. Power supply voltage is applied NF = 1.2 dB to both the output terminal and a separate V terminal. D Gain = 18.4 dB A simple external bias insertion circuit consisting of a OIP3 = 19 dBm shunt inductor and a series dc block capacitor is suf- At3 V,20.5 mA, 5.25 GHz: ficient to apply power supply voltage to the output of NF= 1.45 dB the MGA-665P8. The MGA-665P8 provides typical device Gain= 16 dB performanceof 1.45 dB noise figure, 16 dB gain and an OIP3 = 18.1dBm OIP3 of +18.1 dBm at 5.25 GHz, at a bias point of 3 V and 20.5mA. Pin Configuration, Top View GND PADDLE POWER DOWN FUNCITON: LOGIC LOW (0-1 V): POWER ON 1: GND 8: UNUSED LOGIC HIGH (2-3 V): POWER OFF NOTES: 2: RF 7: RF & V IN OUT D 1. PINS 1, 3, AND PADDLE NEED TO BE PROPERLY GROUNDED TO OBTAIN SPECIFIED PERFORMANCE. 3: GND 6: V D 2. SUPPLY VOLTAGE, V , NEEDS TO BE D APPLIED AT PINS 6 & 7. SUPPLY AT PIN 7 TO BE APPLIED USING A BIAS 4: UNUSED 5: POWERDOWN TEE OR EQUIVALENT. Attention: Observepr ecautions for handling electrostatic sensitive devices. ESDM achine Model = 40 V ESD Human B ody Model =150 V Refert oA vago Application Note A004R: Electrostatic Discharge, Damage and Control. 1 Table 1. Absolute Maximum Ratings Symbol Parameter Units Absolute Maximum 2 V Supply Voltage V 6 D 2 V Control Voltage V 6 C 2 I DrainC urrent mA 45.6 D 3 Pdiss Total Power Dissipation W 0.27 Pin max. RF Input Power dBm 13 T Channel Temperature C 150 CH T Storage Temperature C -65 to 150 STG 4 q Thermal Resistance C/W 44.76 ch b Notes: 1. Operation ofthis device above anyone of these parameters maycause per manent damage. 2. DC quiescentc onditions. 3. Board (package belly) temperature T is 25C.D erate 29 mW/C for T >133C. B B 4. Channel-to-board thermalr esistance measured using 150CLiquid C rystal Measurement method. 5,6 Product Consistency Distribution Charts at 5.25 GHz, 3.0 V, Id = 20.5 mA 160 180 Stdev = 0.23 Stdev = 0.067 150 120 120 3 Std +3 Std 80 90 60 40 30 0 0 1.2 1.3 1.4 1.5 1.6 1.7 17 17.5 18 18.5 19 OIP3 (dBm) NF (dB) Figure 1. NF nominal = 1.45. Figure 2. OIP3 LSL = 17.8, nominal = 18.2. 400 180 Stdev = 0.20 Stdev = 0.11 150 300 120 3 Std +3 Std 3 Std +3 Std 90 200 60 100 30 0 0 15 16 17 11 11.5 12 GAIN (dB) P1dB (dBm) Figure 3. Gain (dB) nominal = 16 dB. Figure 4. P1dB LSL = 11, nominal = 11.4. Notes: 5. Distributionda tasample size is 500 samplestaken fr om3 diff erent wafers lots. Future wafers allocated tothis productma y have nominal val - uesan ywherebet weenthe upper andlo wer limits. 6. Measurements are made on production test boarddescr ibedin Figure 5, which represents a trade-offbet ween optimalOIP3, P1dB , Gain and NF. Circuitlosses havebeen de-embeddedfr om actual measurements 2 FREQUENCY FREQUENCY FREQUENCY FREQUENCY