71x MGA-71543 Low Noise Amplifier with Mitigated Bypass Switch Data Sheet Description Features Avagos MGA-71543 is an economical, easy-to-use GaAs Lead-free Option Available MMIC Low Noise Amplifier (LNA), which is designed for Operating frequency: 0.1 GHz ~ 6.0 GHz adaptive CDMA and W-CDMA receiver systems. The MGA- Noise figure: 0.8 dB (NFmin) 71543 is part of the Avago Technologies complete CD- MAdvantage RF chipset. Gain: 16 dB Average Idd = 2mA in CDMA handset The MGA-71543 features a minimum noise figure of 0.8 dB and 16 dB available gain from a single stage, feedback FET Bypass switch on chip Loss = -5.6 dB (Id < 5 A) IIP3 = amplifier. The input and output are partially matched, and +35 dBm only a simple series/shunt inductor match is required to Adjustable input IP3: 0 to +9 dBm achieve low noise figure and VSWR into 50. 2.7 V to 4.2V operation When set into the bypass mode, both input and output are internally matched through a mitigative circuit. This Applications circuit draws no current, yet duplicates the in and out im- CDMA (IS-95, J-STD-008) Receiver LNA pedance of the LNA. This allows the system user to have Transmit Driver Amp minimum mismatch change from LNA to bypass mode, which is very important when the MGA-71543 is used be- W-CDMA Receiver LNA tween duplexers and/or filters. TDMA (IS-136) handsets The MGA-71543 offers an integrated solution of LNA with adjustable IIP3. The IIP3 can be fixed to a desired current Attention: level for the receivers linearity requirements. Observe precautions for handling electrostatic sensitive devices. The LNA has a bypass switch function, which provides low ESD Machine Model (Class A) insertion loss at zero current. The bypass mode also boosts ESD Human Body Model (Class 0) Refer to Avago Application Note A004R: dynamic range when high level signal is being received. Electrostatic Discharge Damage and Control. The MGA-71543 is designed for CDMA and W-CDMA re- ceiver systems. The IP3, Gain, and mitigative network are Surface Mount Package SOT-343 /4-lead SC70 tailored to these applications where filters are used. Many CDMA systems operate 20% LNA mode, 80% bypass. With the bypass current draw of zero and LNA of 10 mA, the MGA-71543 allows an average 2 mA current. The MGA-71543 is a GaAs MMIC, processed on Avagos cost effective PHEMT (Pseudomorphic High Electron Mo - bility Transistor Technology). It is housed in the SOT343 (SC70 4-lead) package. Pin Connections and Package Marking 3 1 INPUT RF Gnd & V ref & V s 71= Unit marking x = Date Code marking 4 2 RF Gnd OUTPUT & V & V s d71 Functional Block Diagram Simplified Schematic Evaluation Test Circuit (single positive bias) 1.5 nH Input + + 2.7 nH RF IN RF OUT Control Output Input Output & V & V ref d Gain FET R bias V Switch & Bias d RF Gnd RF Gnd control & Vs 1 MGA-71543 Absolute Maximum Ratings 2, 3 Thermal Resistance: Symbol Parameter Units Absolute Operation = 240C/W jc Maximum Maximum Notes: 4 V Maximum Input to Output Voltage V 5.5 4.2 d 1. Operation of this device in excess of any of 4 these limits may cause permanent damage. V Maximum Input to Ground DC Voltage V +.3 +.1 c 2. Ground lead temperature at 25C. -5.5 -4.2 3. Thermal resistance measured by 150C Liquid I Supply Current mA 60 50 Crystal Measurement method. d 4. Maximum rating assumes other parameters 2 P Power Dissipation mW 240 200 d are at DC quiescent conditions. P CW RF Input Power dBm +15 +10 in T Junction Temperature C 170 150 j T Storage Temperature C -65 to +150 -40 to +85 STG 5,6 Product Consistency Distribution Charts 150 150 150 Cpk = 2.00 Cpk = 2.33 Cpk = 1.16 Std = 0.24 Std = 0.02 Std = 0.96 120 120 120 90 90 90 +3 Std +3 Std -3 Std +3 Std -3 Std -3 Std 60 60 60 30 30 30 0 0 0 14.4 15.4 16.4 17.4 13264 5 78 0.85 0.95 1.05 1.15 1.25 1.35 1.45 GAIN (dB) NF (dB) IIP3 (dBm) Figure 3. NF 2 GHz, 3V, 10 mA. Figure 1. Gain 2 GHz, 3V, 10 mA. Figure 2. IIP3 2 GHz, 3V, 10 mA. LSL = 0.85, Nominal = 1.08, USL = 1.45 LSL = 14.4, Nominal = 15.9, USL = 17.4 LSL = 1.0, Nominal = 3.0, USL = 8.0 Notes: 5. Distribution data sample size is 450 samples Excess circuit losses have been de-embedded taken from 9 different wafers. Future wafers from actual measurements. Performance may allocated to this product may have nominal be optimized for different bias conditions and values anywhere within the upper and lower applications. Consult Application Note for specification limits. details. 6. Measurements made on production test board, Figure 4. This circuit represents a trade-off between an optimal noise match and a realizable match based on production test requirements at 10 mA bias current. 2 2 FREQUENCY FREQUENCY FREQUENCY