MGA-72543-BLKG Broadcom

72x MGA-72543 PHEMT* Low Noise Amplifi er with Bypass Switch Data Sheet Description Features Lead-free Option Available Avagos MGA-72543 is an economical, easy-to-use GaAs Operating Frequency: 0.1 GHz ~ 6.0 GHz MMIC Low Noise Amplifi er (LNA),which is designed for an adaptive CDMA receiver LNA and adaptive CDMA transmit Noise Figure: 1.4 dB at 2 GHz driver amplifi er. Gain: 14 dB at 2 GHz The MGA-72543 features a minimum noise fi gure of 1.4 dB Bypass Switch on Chip Loss = -2.5 dB (Id <5 A) and 14 dB associated gain from a single stage, feedback IIP3 = +35 dBm FET amplifi er. The output is internally matched to 50. Adjustable Input IP3: +2 to +14 dBm The input is optimally internally matched for lowest noise 2.7 V to 4.2 V Operation fi gure into 50. The input may be additionally externally matched for low VSWR through the addition of a single Very Small Surface Mount Package series induc tor. When set into the bypass mode,both input and output are internally matched to 50. Applications The MGA-72543 off ers an integrated solution of LNA with CDMA (IS-95, J-STD-008) Receiver LNA Transmit adjustable IIP . The IIP can be fi xed to a desired current 3 3 Driver Amp level for the receivers linearity requirements. The LNA has TDMA (IS-136)Handsets a bypass switch function,which sets the current to zero and provides low insertion loss. The bypass mode also boosts dynamic range when high level signal is being Surface Mount Package received. SOT-343 (SC-70) For the CDMA driver amplifi er applications, the MGA- 72543 provides suitable gain and linearity to meet the ACPR requirements when the handset transmits the highest power. When transmitting lower power, the MGA- 72543 can be bypassed, saving the drawing current. The MGA-72543 is a GaAs MMIC, processed on Avagos cost eff ective PHEMT (Pseudomorphic High Electron Mo- Pin Connections and Package Marking bility Transistor). It is housed in the SOT343 (SC70 4-lead) package, and is part of the Avago Technologies CDMAd- 3 1 vantage RF chipset. INPUT GND & V ref 4 2 Attention: Observe precautions for OUTPUT GND & V d handling electrostatic sensitive devices. ESD Machine Model (Class A) ESD Human Body Model (Class 0) Package marking is 3 characters. The last character represents date code. Refer to Avago Application Note A004R: Electrostatic Discharge Damage and Control. *Pseudomorphic High Electron Mobility Transistor 1 MGA-72543 Absolute Maximum Ratings Symbol Parameter Units Absolute Operation Maximum Maximum V Maximum Input to Output Voltage V 5.5 4.2 d V Maximum Input to Ground DC Voltage V +0.3 +0.1 ref -5.5 -4.2 I Supply Current mA 70 60 d 2,3 P Power Dissipation mW 300 250 d P CW RF Input Power dBm +20 +13 in T Junction Temperature C 170 150 j T Storage Temperature C -65 to +150 -40 to +85 STG 2 Thermal Resistance: = 200C/W jc Notes: 1. Operation of this device in excess of any of these limits may cause permanent damage. 2. Tcase = 25C. Simplifi ed Schematic Functional Block Diagram RF IN RF OUT Control Input Output & & V d V ref SW & Bias Control GainFET GND GND 2