VMMK-2103 0.5 to 6 GHz Bypass E-pHEMT LNA in Wafer Level Package Data Sheet Description Features Avagos VMMK-2103 is an easy-to-use GaAs MMIC bypass 1 x 0.5 mm Surface Mount Package LNA that offers good noise figure and flat gain from 0.5 to Ultrathin (0.25mm) 6 GHz in a miniaturized wafer-level package (WLP). The LNA Bypass function bias circuit incorporates a power down feature which is accessed from the input port. This device contains an in- 5V Supply tegrated bypass switch which engages when the amplifier RoHS6 + Halogen Free is in shut down mode, resulting in an improvement in the input compression point while consuming minimal Specifications (at 3GHz, Vd = Vc = 5V, 23mA Typ.) current. Noise Figure: 2.1dB typical The input and output are matched to 50 (better than 2:1 Loss in Bypass Mode: 2.3dB SWR) across the entire bandwidth no external matching Associated Gain: 14dB is needed. This amplifier is fabricated with enhancement E-pHEMT technology and industry leading wafer level Input IP3 in Gain Mode: +8dBm package. The WLP leadless package is small and ultra thin Input IP3 in Bypass Mode: +21 dBm yet can be handled and placed with standard 0402 pick Input P1dB in Gain Mode: 0dBm and place assembly. Input P1dB in Bypass Mode: +17dBm WLP 0402, 1mm x 0.5mm x 0.25 mm Applications Low Noise and Driver for Cellular/PCS and WCDMA Base Stations 2.4 GHz, 3.5GHz, 5-6GHz WLAN and WiMax notebook computer, access point and mobile wireless applications 802.16 & 802.20 BWA systems Pin Connections (Top View) WLL and MMDS Transceivers Radar, radio and ECM Systems Input Output CY / Vc / Vdd Attention: Observe precautions for handling electrostatic sensitive devices. ESD Machine Model =50V Input Output ESD Human Body Model =125V Amp / Vc / Vdd Refer to Avago Application Note A004R: Electrostatic Discharge, Damage and Control. Note: C = Device Code Y = Month Code CY 1 Table 1. Absolute Maximum Ratings Sym Parameters/Condition Unit Absolute Max 2 Vd Supply Voltage (RF Output) V 8 Vc Bypass Control Voltage V 6 2 Id Device Current mA 40 3 P CW RF Input Power (RF Input) dBm +20 in, max P Total Power Dissipation mW 320 diss Tch Max channel temperature C 150 4 jc Thermal Resistance C/W 110 Notes 1. Operation in excess of any of these conditions may result in permanent damage to this device. 2. Bias is assumed DC quiescent conditions 3. With the DC (typical bias in both modes) and RF applied to the device at board temperature Tb = 25C 4. Thermal resistance is measured from junction to board using IR method Table 2. DC and RF Specifications T = 25C, Frequency = 3 GHz, Vd = 5V, Vc=5V, Z =Z =50 (unless otherwise specified) A in out Sym Parameters/Condition Unit Minimum Typ. Maximum Id Device Current mA 16 23 30 6 Id leakage Current in Bypass Mode mA 0.6 1.5 1 NF Noise Figure dB 2.1 2.7 1 Ga Associated Gain dB 12 14 16 1,6 Ga Bypass Associated Gain in Bypass Mode dB -4.1 -2.3 2,3 IIP3 Gain Input IP3 in Gain Mode dBm 8 2,4,6 IIP3 Bypass Input IP3 in Bypass Mode dBm 21 2 IP1dB Gain Input P1dB in Gain Mode dBm 0 2,6 IP1dB Bypass Input P-1dB in Bypass Mode 17 2 IRL Input Return Loss dB -11 2 ORL Output Return Loss dB -13 5 ts Switching Time s 0.1 Notes: 1. Measure data obtained using 300um G-S production wafer probe 2. Measure data obtained using 300um G-S-G PCB probe on substrate 3. IIP3 test condition: F1 = 3.0GHz, F2 = 3.01GHz, Pin = -10dBm in Gain Mode for typical performance during characterization 4. IIP3 test condition: F1 = 3.0GHz, F2 = 3.01GHz, Pin = 0dBm in Bypass Mode for typical performance during characterization 5. Switching time measured using test board (Figure 20) 6. Bypass Mode Bias Voltages are Vd = 5V, Vc = 0V 2