THCS251 Rev.3.00 E THCS251 35-bits GPIO or high speed Bus signal Transceiver General description Features Support up to 35-bits GPIO The THCS251 integrates Serializer and Deserializer Not required to input GPIO sampling clock in onto a single chip, which supports general purpose internal oscillator clock mode input and output (GPIO) signals through two pairs of Full duplex communication by two pairs of differential signal. differential signal Output buffer open-drain or push-pull selectable GPIO sampling clock is selectable from external Support up to 8-bits low speed GPIO in low reference clock or internal oscillator clock. power Standby mode Integrated adaptive equalizer for long or lossy The 8B10B encoding and decoding adopted by media THCS251 is easy to connect to optical / wireless 8B10B encoding and decoding communication devices with high robustness and DC Configurable digital noise filter balanced signal. Error detection and indication External reference clock frequency: 9-100MHz The built-in adaptive equalizer enables flexible cable Spread Spectrum Clock Generator to reduce EMI selection. Operating single power supply voltage: 1.7 V - 3.6 V Application Wide range IO voltage: 1.7V - 3.6V The THCS251 can applicable to any systems which Operating temperature: -40C to 85C have many control signals between PCBs, for example Multi-function printers, Amusement machines, Factory Automation and TVs. Block diagram THCS251 (Master mode) THCS251 (Slave mode) REFEN LDO OSC SSCG PLL REFIN TXP RXP TXN RXN GPIO GPIO D34/D0 D0/D34 .... D0/D34 D34/D0 REFOUT TXN RXN RXP TXP PLL LDO SSCG OSC Copyright 2 0 21 THine Electronics, Inc. THine Electronics, Inc. 1/32 SC: E LVCMOS I/O Formatter Rx Tx (Deserializer) (Serializer) Tx Rx (Serializer) (Deserializer) Formatter LVCMOS I/OTHCS251 Rev.3.00 E Contents page General description.................................................................................................................................................. 1 Application .............................................................................................................................................................. 1 Features ................................................................................................................................................................... 1 Block diagram ......................................................................................................................................................... 1 1. Pin configuration ............................................................................................................................................. 3 2. Pin description ................................................................................................................................................. 4 3. Absolute maximum ratings.............................................................................................................................. 8 4. Recommended operating conditions ............................................................................................................... 8 5. Electrical characteristics .................................................................................................................................. 9 5.1. Current consumption ............................................................................................................................... 9 5.2. LVCMOS/Analog input DC specifications ........................................................................................... 10 5.3. LVCMOS AC characteristics ................................................................................................................. 11 5.4. CML DC characteristics ........................................................................................................................ 14 5.5. CML AC characteristics ........................................................................................................................ 14 6. CML Line Eye diagrams ............................................................................................................................... 19 6.1. CML output Eye diagrams..................................................................................................................... 19 6.2. CML input Eye diagrams ...................................................................................................................... 20 7. Function ......................................................................................................................................................... 21 7.1. Functional overview .............................................................................................................................. 21 7.2. Power supply ......................................................................................................................................... 21 7.2.1. Internal regulator output/input function (CAPOUT, CAPINA, CAPINP) .................................... 21 7.3. Operating mode ..................................................................................................................................... 21 7.4. Transmission mode ................................................................................................................................ 22 7.4.1. Full duplex Bi-directional transmission mode ............................................................................... 22 7.4.2. Unidirectional transmission mode ................................................................................................. 24 7.5. IO configuration .................................................................................................................................... 25 7.5.1. Input and Output digital noise filter .............................................................................................. 25 7.5.2. LVCMOS output buffer type configuration ................................................................................... 25 7.5.3. 5V Tolerant I/O .............................................................................................................................. 25 7.6. Sampling clock configuration ................................................................................................................ 26 7.6.1. Sampling clock selection ............................................................................................................... 26 7.6.2. Spread Spectrum Clock Generator (SSCG) and REFIN frequency............................................... 28 7.7. Error detection and indication ............................................................................................................... 29 7.8. Standby mode ........................................................................................................................................ 30 8. Package .......................................................................................................................................................... 31 Notices and Requests ............................................................................................................................................. 32 Copyright 2 0 21 THine Electronics, Inc. THine Electronics, Inc. 2/32 SC: E