CS2000CP-EZZ Cirrus Logic

CS2000-CP Fractional-N Clock Synthesizer & Clock Multiplier The CS2000-CP is an extremely versatile system Features clocking device that utilizes a programmable phase Delta-Sigma Fractional-N Frequency Synthesis lock loop. The CS2000-CP is based on a hybrid ana- Generates a Low Jitter 6 - 75 MHz Clock log-digital PLL architecture comprised of a unique from an 8 - 75 MHz Reference Clock combination of a Delta-Sigma Fractional-N Frequency Clock Multiplier / Jitter Reduction Synthesizer and a Digital PLL. This architecture allows Generates a Low Jitter 6 - 75 MHz Clock for both frequency synthesis/clock generation from a from a Jittery or Intermittent 50 Hz to stable reference clock as well as generation of a low- 30 MHz Clock Source jitter clock relative to an external noisy synchronization Highly Accurate PLL Multiplication Factor clock. The design is also unique in that it can generate low-jitter clocks relative to noisy external synchroniza- Maximum Error Less Than 1 PPM in High- Resolution Mode tion clocks at frequencies as low as 50 Hz. The CS2000-CP supports both IC and SPI for full software IC / SPI Control Port control. Configurable Auxiliary Output The CS2000-CP is available in a 10-pin MSOP Flexible Sourcing of Reference Clock package in Commercial (-10C to +70C), Automotive- External Oscillator or Clock Source D (-40C to +85C), and Automotive-E (-40C to Supports Inexpensive Local Crystal +105C) grades. Customer development kits are also Minimal Board Space Required available for device evaluation. Please see Ordering No External Analog Loop-filter Information on page 36 for complete details. Components 3.3 V Timing Reference IC/SPI Frequency Reference IC / SPI Auxiliary Software Control PLL Output Output Lock Indicator 8 MHz to 75 MHz Fractional-N 6 to 75 MHz Low-Jitter Timing Frequency Synthesizer PLL Output Reference N Output to Input Clock Ratio 50 Hz to 30 MHz Digital PLL & Fractional Frequency N Logic Reference Output to Input Clock Ratio Copyright Cirrus Logic, Inc. 20092015 SEPT 15 (All Rights Reserved) CS2000-CP TABLE OF CONTENTS 1. PIN DESCRIPTION ................................................................................................................................. 5 2. TYPICAL CONNECTION DIAGRAM ..................................................................................................... 6 3. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 7 RECOMMENDED OPERATING CONDITIONS .................................................................................... 7 ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 7 DC ELECTRICAL CHARACTERISTICS ................................................................................................ 7 AC ELECTRICAL CHARACTERISTICS ................................................................................................ 8 PLL PERFORMANCE PLOTS ............................................................................................................... 9 CONTROL PORT SWITCHING CHARACTERISTICS- IC FORMAT ................................................. 10 CONTROL PORT SWITCHING CHARACTERISTICS - SPI FORMAT ............................................... 11 4. ARCHITECTURE OVERVIEW ............................................................................................................. 12 4.1 Delta-Sigma Fractional-N Frequency Synthesizer ......................................................................... 12 4.2 Hybrid Analog-Digital Phase Locked Loop ....................................................................................12 4.2.1 Fractional-N Source Selection for the Frequency Synthesizer .............................................. 13 5. APPLICATIONS ................................................................................................................................... 14 5.1 Timing Reference Clock Input ........................................................................................................ 14 5.1.1 Internal Timing Reference Clock Divider ............................................................................... 14 5.1.2 Crystal Connections (XTI and XTO) ...................................................................................... 15 5.1.3 External Reference Clock (REF CLK) .................................................................................. 15 5.2 Frequency Reference Clock Input, CLK IN ................................................................................... 15 5.2.1 CLK IN Skipping Mode ......................................................................................................... 15 5.2.2 Adjusting the Minimum Loop Bandwidth for CLK IN ............................................................17 5.3 Output to Input Frequency Ratio Configuration ............................................................................. 19 5.3.1 User Defined Ratio (RUD), Frequency Synthesizer Mode .................................................... 19 5.3.2 User Defined Ratio (RUD), Hybrid PLL Mode ....................................................................... 19 5.3.3 Ratio Modifier (R-Mod) .......................................................................................................... 20 5.3.4 Effective Ratio (REFF) .......................................................................................................... 20 5.3.5 Fractional-N Source Selection ............................................................................................... 21 5.3.6 Ratio Configuration Summary ............................................................................................... 22 5.4 PLL Clock Output ........................................................................................................................... 23 5.5 Auxiliary Output .............................................................................................................................. 23 5.6 Clock Output Stability Considerations ............................................................................................ 24 5.6.1 Output Switching ................................................................................................................... 24 5.6.2 PLL Unlock Conditions .......................................................................................................... 24 5.7 Required Power Up Sequencing .................................................................................................... 24 6. SPI / IC CONTROL PORT ................................................................................................................... 24 6.1 SPI Control ..................................................................................................................................... 25 6.2 IC Control ...................................................................................................................................... 25 6.3 Memory Address Pointer ............................................................................................................... 27 6.3.1 Map Auto Increment .............................................................................................................. 27 7. REGISTER QUICK REFERENCE ........................................................................................................ 27 8. REGISTER DESCRIPTIONS ................................................................................................................ 28 8.1 Device I.D. and Revision (Address 01h) ........................................................................................ 28 8.1.1 Device Identification (Device 4:0 ) - Read Only ..................................................................... 28 8.1.2 Device Revision (Revision 2:0 ) - Read Only ........................................................................ 28 8.2 Device Control (Address 02h) ........................................................................................................ 28 8.2.1 Unlock Indicator (Unlock) - Read Only .................................................................................. 28 8.2.2 Auxiliary Output Disable (AuxOutDis) ................................................................................... 28 8.2.3 PLL Clock Output Disable (ClkOutDis) .................................................................................. 29 8.3 Device Configuration 1 (Address 03h) ........................................................................................... 29 8.3.1 R-Mod Selection (RModSel 2:0 ) ...........................................................................................29 8.3.2 Ratio Selection (RSel 1:0 ) .................................................................................................... 29 2 DS761F3