CS2300-02 1x, 2x, 4x, and 8x Clock Multiplier with Internal LCO Features Ordering Information Clock Multiplier / Jitter Reduction The CS2300-02 is available in a 10-pin MSOP package in Commercial (-10C to +70C) grade. Customer de- Generates a Low Jitter 6 - 75 MHz Clock velopment kits are also available for custom device from a Jittery 750 kHz to 30 MHz Clock prototyping and device evaluation. Please see Order- Source ing Information on page 2 for complete details. Internal LCO Reference Clock 128 Hz Loop Filter Bandwidth Pin-Out Diagram Selectable Multiplication Factors 1x, 2x, 4x, and 8x 10 M0 VD 1 Output Enable Pin 9 GND 2 M1 Lock Indicator CLK OUT 3 8 OUT EN Minimal Board Space Required 7 FILTN LOCK 4 5 FILTP No External Analog Loop-filter CLK IN 6 Components Hardware Controls Settings General Description The CS2300-02 is an extremely versatile system clock- M1 M0 PLL OUT ing device that utilizes a programmable phase lock loop. 00 1x CLK IN The CS2300-02 is based on a hybrid analog-digital PLL 01 2x CLK IN architecture comprised of a unique combination of a 10 4x CLK IN Delta-Sigma Fractional-N Frequency Synthesizer and a 11 8x CLK IN Digital PLL. This architecture allows for generation of a low-jitter clock relative to an external noisy synchroniza- tion clock with frequencies as low as 750 kHz. The OUT EN CLK OUT CS2300-02 is a CS2300-OTP device that has been pre- 0 Enabled configured at the factory. There are three hardware con- 1 High Impedance figuration pins available for mode and feature selection. FILTP LOCK 0.1 F PLL Lock LCO Indicator FILTN Fractional-N Frequency Synthesizer CLK OUT 6 MHz to 75 MHz M 1:0 PLL Output M1 00=1x N Ratio Selection M0 01=2x OUT EN Output 10=4x Enable/Disable 11=8x Output to Input VD 3.3 V Clock Ratio 128 Hz BW Digital PLL 0.1 F 1 F & Fractional N Logic CLK IN 750 kHz to 30 MHz GND Frequency Reference This document contains information for a new product. Advance Product Information Cirrus Logic reserves the right to modify this product without notice. Copyright Cirrus Logic, Inc. 2008 February 08 (All Rights Reserved) CS2300-02 1. PIN DESCRIPTIONS 2. SPECIFICATIONS Please see the CS2300-OTP datasheet for package in- Pin Name Pin Description formation, device characteristics, and specifications ex- VD 1 Digital Power cept where noted due to specific programming options. GND 2 Ground CLK OUT 3 PLL Clock Output 3. OPERATIONAL INFORMATION LOCK 4 Active Low PLL Lock Indicator Complete operational information can be found in the CLK IN 5 Clock Input CS2300-OTP datasheet. Specific operational details FILTP 6 LCO Filter Connections dictated by the programming of the CS2300-02 are in- FILTN 7 cluded below. OUT EN 8 Active Low CLK OUT Enable Input The PLL clock output is forced to 0 when the PLL is M1 9 Mode Selection Inputs unlocked, both upon loss of the CLK IN signal or M0 10 briefly when switching mode pin configurations. See the CS2300-OTP datasheet for additional pin de- The minimum loop filter bandwidth once locked is scription information. 128 Hz. 4. CONFIGURATION INFORMATION The CS2300-02 has been factory pre-programmed with a unique configuration. The following table outlines the spe- cific configuration profile which can be compared to the CS2300-OTP datasheet for detailed functional descriptions. OTP Modal and Global Configuration Parameters Form Mode 0 Mode 1 Mode 2 Mode 3 Ratio 0 (dec) 12 4 8 Ratio 0 (hex) 00:10:00:00 00:20:00:00 00:40:00:00 00:80:00:00 RModSel1 00 0 0 RModSel0 00 0 0 AuxOutSrc1 11 1 1 AuxOutSrc0 11 1 1 AutoRMod 00 0 0 Global Configuration Set ClkSkipEn AuxLockCfg ClkOutUnl LFRatioCfg M2Cfg2 M2Cfg1 M2Cfg0 0 0 0 1 0 0 0 ClkIn BW2 ClkIn BW1 ClkIn BW0 1 1 1 5. ORDERING INFORMATION Product Description Package Pb-Free Grade Temp Range Container Order Rail CS230002-CZZ CS2300-02 Clocking Device 10L-MSOP Yes Commercial -10 to +70C Tape and CS230002-CZZR Reel CDK-2000 Evaluation Platform - Yes - - - CDK-2000-LCO PS855A1 2