CS4207 Low-power, 4-in / 6-out HD Audio Codec with Headphone Amp DIGITAL to ANALOG FEATURES ANALOG to DIGITAL FEATURES DAC1 (Headphone) ADC1 & ADC2 101 dB Dynamic Range (A-wtd) 105 dB Dynamic Range (A-wtd) -89 dB THD+N -88 dB THD+N Differential Balanced or Single-ended Headphone Amplifier - GND Centered Inputs Integrated Negative-voltage Regulator Analog Programmable Gain Amplifier No DC-blocking Capacitor Required (PGA) 12 dB, 1.0 dB Steps, with Zero 50 mW Power/Channel into 16 Cross Transitions and Mute DAC2 & DAC3 (Line Outs) MIC Inputs 110 dB Dynamic Range (A-wtd) Pre-amplifier with Selectable 0 dB, +10 dB, -94 dB THD+N +20 dB, and +30 dB Gain Settings Differential Balanced or Single-ended Programmable, Low-noise MIC Bias Level Each DAC Supports 32 kHz to 192 kHz Sample Rates Independently. Each ADC Supports 8 kHz to 96 kHz Sample Rates Independently Digital Volume Control +6.0 dB to -57.5 dB in 0.5 dB Steps Additional Digital Attenuation Control Zero Cross and/or Soft Ramp Transitions -13.0 dB to -51.0 dB in 1.0 dB steps Independent Support of D0 and D3 Power Zero Cross and/or Soft Ramp Transitions States for Each DAC Digital Interface for Two Dual Digital Mic Inputs Fast D3 to D0 Transition Audio Playback in Less Than 50 ms Independent Support of D0 and D3 Power States for Each ADC VD VA, VA REF VA HP (1.5 V to 1.8 V) (3.3 V to 5.0 V) (3.3 V to 5.0 V) Chrg Chrg Pump Pump Buck Invert +VHP -VHP Headphone SRC & Left HP Out 2-Chnl Vol/Mute Multibit Amp - GND DAC1 Right HP Out Modulator Centered HD HD Audio + Audio Left Line Out Bus SRC & Line - Interface 2-Chnl Vol/Mute Multibit Out DAC2 + VL HD Modulator Right Line Out - (1.5 V to 3.3 V) + Left Line Out SRC & Line - 2-Chnl Vol/Mute Multibit Out GPIO GPIO DAC3 + Modulator Right Line Out - SPDIF S/PDIF OUT 2 + TX 2 Digital Vol/Boost/ Line/Mic In L 2-Chnl - Filter & PGA SPDIF Mute ADC1 Line/Mic In R S/PDIF OUT 1 SRC TX 1 + HD Bus VL IF Fs + 128Fs Clock Digital Mic/Line In L Vol/Boost/ 2-Chnl (3.3 V) - Multiplier PGA Filter & Mute ADC2 + Mic/Line In R SRC - SPDIF SPDIF S/PDIF IN MIC RX RX SRC Mic Bias Bias D-Mic Clock Jack SENSE A D-Mic In Sense Copyright Cirrus Logic, Inc. 2012 AUG 12 (All Rights Reserved) CS4207 Digital Audio Interface Receiver General Description Complete EIAJ CP1201, IEC 60958, S/PDIF The CS4207 is a highly integrated multi-channel low- Compatible Receiver power HD Audio Codec featuring 192kHz DACs, 96 kHz ADCs, 192 kHz S/PDIF Transmitters and Re- 32 kHz to 192 kHz Sample Rate Range ceiver, Microphone pre-amp and bias voltage, and a Automatic Detection of Compressed Audio ground centered Headphone driver. Based on multi-bit, Streams delta-sigma modulation, it allows infinite sample rate adjustment between 32 kHz and 192 kHz. Integrated Sample Rate Converter The ADC input path allows control of a number of fea- 128 dB Dynamic Range tures. The microphone input path includes a selectable -120 dB THD+N programmable-gain pre-amplifier stage and a low-noise Supports Sample Rates up to 192 kHz MIC bias voltage supply. A PGA is available for line and 1:1 Input/Output Sample Rate Ratios microphone inputs and provides analog gain with soft ramp and zero cross transitions. The ADC also features Digital Audio Interface Transmitters an additional digital volume attenuator with soft ramp Two Independent EIAJ CP1201, IEC-60958, transitions. S/PDIF Compatible Transmitters The stereo headphone amplifier is powered from a sep- 32 kHz to 192 kHz Sample Rate Range arate internally generated positive supply, with an integrated charge pump providing a negative supply. System Features This allows a ground-centered analog output with a wide signal swing and eliminates external DC-blocking Very Low D3 Power Dissipation of <7 mW capacitors. Jack Detect Active in D3 The integrated digital audio interface receiver and trans- HDA BITCLK Not Required for D3 State mitters utilize a 24-bit, high-performance, monolithic Jack Detect Does Not Require HDA Bus CMOS stereo asynchronous sample rate converter to BITCLK clock align the PCM samples to/from the S/PDIF inter- faces. Auto detection of non-PCM encoded data All Configuration Settings are Preserved in D3 disables the sample rate conversion to preserve bit ac- State curacy of the data. Pop/Click Suppression in State Transitions In addition to its many features, the CS4207 operates Detects Wake Event and Generates Power from a low-voltage analog and digital core, making this State Change Request when HDA Bus part ideal for portable systems that require low power Controller is in D3 consumption in a minimal amount of space. Variable Power Supplies 1.5 V to 1.8 V Digital Core Voltage The CS4207 is available in a 48-pin WQFN package in both Automotive (-40C to +105C) and Commercial 3.3 V to 5.0 V Analog Core Voltage (-40C to +85C) grades. The CS4207 Customer Dem- 3.3 V to 5.0 V Headphone Drivers onstration board is also available for device evaluation 1.5 V to 3.3 V HD Bus Interface Logic and implementation suggestions. Please refer to Or- 3.3 V Interface Logic levels for GPIO, dering Information on p147 for complete ordering information. S/PDIF, and Digital Mic Individual Power-down Managed ADCs, DACs, PGAs, Headphone Driver, S/PDIF Receiver, and Transmitters 2 DS880F4