CS5521/22/23/24/28 16-bit or 24-bit, 2/4/8-channel ADCs with PGIA Features General Description The CS5521/22/23/24/28 are highly integrated ana- Low Input Current (100 pA), Chopper- log-to-digital converters (ADCs) which use charge- stabilized Instrumentation Amplifier balance techniques to achieve 16-bit (CS5521/23) and Scalable Input Span (Bipolar/Unipolar) 24-bit (CS5522/24/28) performance. The ADCs come as - 2.5V VREF: 25 mV, 55 mV, 100 mV, 1 V, either two-channel (CS5521/22), four-channel 2.5 V, 5 V (CS5523/24), or eight-channel (CS5528) devices and include a low-input-current, chopper-stabilized instru- - External: 10 V, 100 V mentation amplifier. To permit selectable input spans of Wide V Input Range (+1 to +5 V) REF 25 mV, 55 mV, 100 mV, 1 V, 2.5 V, and 5 V, the ADCs Fourth Order Delta-Sigma A/D Converter include a PGA (programmable gain amplifier). To ac- Easy to Use Three-wire Serial Interface Port commodate ground-based thermocouple applications, the devices include a charge pump drive which provides - Programmable/Auto Channel Sequencer with a negative bias voltage to the on-chip amplifiers. Conversion Data FIFO - Accessible Calibration Registers per Channel These devices also include a fourth-order modulator followed by a digital filter which provides eight selectable - Compatible with SPI and Microwire output word rates. The digital filters are designed to settle System and Self Calibration to full accuracy within one conversion cycle and when Eight Selectable Word Rates operated at word rates below 30 Sps, they reject both 50 Hz and 60 Hz interference. - Up to 617 Sps (XIN = 200 kHz) - Single Conversion Settling These single-supply products are ideal solutions for - 50/60 Hz 3 Hz Simultaneous Rejection measuring isolated and non-isolated, low-level signals in process control applications. Single +5 V Power Supply Operation - Charge Pump Drive for Negative Supply - +3 to +5 V Digital Supply Operation ORDERING INFORMATION Low Power Consumption: 6.0 mW See page 53. VA+ AGND VREF+ VREF- DGND VD+ X1 Controller, X1 AIN1+ Setup Registers, Digital Filter Differential & AIN1- + th Channel Scan 4 Order X20 AIN2+ Logic AIN2- Modulator X1 MUX CS5524 AIN3+ Shown CS AIN3- Serial Port SCLK AIN4+ Interface Data FIFO & AIN4- Clock SDI Latch Calibration Registers Gen. SDO NBV CPD A0 A1 XIN XOUT JUL 09 Copyright Cirrus Logic, Inc. 2009 CS5521/22/23/24/28 TABLE OF CONTENTS ANALOG CHARACTERISTICS................................................................................................ 5 TYPICAL RMS NOISE, CS5521/23.......................................................................................... 7 TYPICAL NOISE FREE RESOLUTION (BITS), CS5521/23 .................................................... 7 TYPICAL RMS NOISE, CS5522/24/28..................................................................................... 8 TYPICAL NOISE FREE RESOLUTION (BITS), CS5522/24/28 ............................................... 8 5 V DIGITAL CHARACTERISTICS........................................................................................... 9 3 V DIGITAL CHARACTERISTICS........................................................................................... 9 DYNAMIC CHARACTERISTICS ............................................................................................ 10 RECOMMENDED OPERATING CONDITIONS ..................................................................... 10 ABSOLUTE MAXIMUM RATINGS ......................................................................................... 10 SWITCHING CHARACTERISTICS ........................................................................................ 11 1. GENERAL DESCRIPTION ..................................................................................................... 13 1.1 Analog Input ..................................................................................................................... 13 1.1.1 Instrumentation Amplifier .........................................................................................14 1.1.2 Coarse/Fine Charge Buffers ............................................................................... 14 1.1.3 Analog Input Span Considerations .......................................................................... 15 1.1.4 Measuring Voltages Higher than 5 V .................................................................. 15 1.1.5 Voltage Reference .............................................................................................. 16 1.2 Overview of ADC Register Structure and Operating Modes ............................................ 16 1.2.1 System Initialization ............................................................................................ 18 1.2.2 Command Register Quick Reference ............................................................... 19 1.2.3 Command Register Descriptions ........................................................................ 20 1.2.4 Serial Port Interface ............................................................................................ 25 1.2.5 Reading/Writing the Offset, Gain, and Configuration Registers ..........................26 1.2.6 Reading/Writing the Channel-Setup Registers ................................................... 26 1.2.6.1 Latch Outputs ...................................................................................... 28 1.2.6.2 Channel Select Bits ............................................................................. 28 1.2.6.3 Output Word Rate Selection ............................................................... 28 1.2.6.4 Gain Bits .............................................................................................. 28 1.2.6.5 Unipolar/Bipolar Bit ............................................................................. 28 1.2.7 Configuration Register ........................................................................................ 28 1.2.7.1 Chop Frequency Select ....................................................................... 28 1.2.7.2 Conversion/Calibration Control Bits ....................................................28 1.2.7.3 Power Consumption Control Bits ........................................................ 28 1.2.7.4 Charge Pump Disable ......................................................................... 29 1.2.7.5 Reset System Control Bits .................................................................. 29 1.2.7.6 Data Conversion Error Flags ............................................................... 29 1.3 Calibration ........................................................................................................................ 31 1.3.1 Self Calibration .................................................................................................... 31 1.3.2 System Calibration .............................................................................................. 32 1.3.3 Calibration Tips ................................................................................................... 34 1.3.4 Limitations in Calibration Range ......................................................................... 34 1.4 Performing Conversions and Reading the Data Conversion FIFO .................................. 34 1.4.1 Conversion Protocol ............................................................................................ 35 1.4.1.1 Single, One-Setup Conversion ............................................................ 35 1.4.1.2 Repeated One-Setup Conversions without Wait ................................. 35 1.4.1.3 Repeated One-Setup Conversions with Wait ...................................... 36 1.4.1.4 Single, Multiple-Setup Conversions .................................................... 36 1.4.1.5 Repeated Multiple-Setup Conversions without Wait ........................... 37 1.4.1.6 Repeated Multiple-Setup Conversions with Wait ................................ 37 1.4.2 Calibration Protocol ............................................................................................. 38 2 DS317F8