WM8974 Mono CODEC with Speaker Driver DESCRIPTION FEATURES Mono CODEC: The WM8974 is a low power, high quality mono CODEC Audio sample rates:8, 11.025, 16, 22.05, 24, 32, 44.1, 48kHz designed for portable applications such as Digital Still Camera DAC SNR 98dB, THD -84dB (A-weighted 8 48ks/s) or Digital Voice Recorder. ADC SNR 94dB, THD -83dB (A-weighted 8 48ks/s) The device integrates support for a differential or single ended On-chip Headphone/Speaker Driver with cap-less connect mic, and includes drivers for speakers or headphone, and - 40mW output power into 16 / 3.3V SPKVDD mono line output. External component requirements are - BTL speaker drive 0.9W into 8 / 5V SPKVDD reduced as no separate microphone or headphone amplifiers Additional MONO Line output are required. Multiple analogue or Aux inputs, plus analogue bypass path Mic Preamps: Advanced Sigma Delta Converters are used along with digital Differential or single end Microphone Interface decimation and interpolation filters to give high quality audio at - Programmable preamp gain sample rates from 8 to 48ks/s. Additional digital filtering - Psuedo-differential inputs with common mode rejection options are available in the ADC path, to cater for application - Programmable ALC / Noise Gate in ADC path filtering such as wind noise reduction, plus an advanced Low-noise bias supplied for electret microphones mixed signal ALC function with noise gate is provided. The digital audio interface supports A-law and -law companding. OTHER FEATURES 5 band EQ (record or playback path) An on-chip PLL is provided to generate the required Master Digital Playback Limiter Clock from an external reference clock. The PLL clock can Programmable ADC High-Pass Filter (wind noise reduction) also be output if required elsewhere in the system. Programmable ADC Notch Filter The WM8974 operates at supply voltages from 2.5 to 3.6V, On-chip PLL although the digital supplies can operate at voltages down to Low power, low voltage 1.71V to save power. The speaker and mono outputs use a - 2.5V to 3.6V (digital: 1.71V to 3.6V) separate supply of up to 5V which enables increased output - power consumption <10mA all-on 48ks/s mode power if required. Different sections of the chip can also be 4x4x0.9mm 24 lead QFN package powered down under software control by way of the selectable APPLICATIONS two or three wire control interface. Digital Still Camera Audio CODEC WM8974 is supplied in a very small 4x4mm QFN package, Wireless VoIP and other communication handsets / headsets offering high levels of functionality in minimum board area, with Portable audio recorder high thermal performance. General Purpose low power audio CODEC analog inputs DCVDD DBVDD DGND AUX SPKGND SPKVDD 20k WM8974 20k ADC DIGITAL DAC Gains: FILTERS DIGITAL -12dB to +35.25dB NOISY FILTERS GND Volume MICN Volume 5 Band EQ ADC DAC MONOOUT 5 Band EQ Limiter / ALC Mic Digital Limiter IP PGA IP BOOST/MIX Wind Noise MICP Filter Notch Filter 0dB, 0dB, Rbias -10dB -10dB SPKOUTP -1 BYPASS L - (-R) = L+R SPKOUTN 2 I S or PCM CONTROL SPKR PGA MICBIAS PLL INTERFACE 50k 50k INTERFACE A-law and u-law support 4k 5k 500k 500k Rev 4.7 Copyright Cirrus Logic, Inc., 2004 2016 AUG 16 WM8974 TABLE OF CONTENTS DESCRIPTION ....................................................................................................... 1 FEATURES ............................................................................................................ 1 APPLICATIONS ..................................................................................................... 1 TABLE OF CONTENTS ......................................................................................... 2 PIN CONFIGURATION .......................................................................................... 3 ORDERING INFORMATION .................................................................................. 3 PIN DESCRIPTION ................................................................................................ 4 ABSOLUTE MAXIMUM RATINGS ........................................................................ 5 RECOMMENDED OPERATING CONDITIONS ..................................................... 5 ELECTRICAL CHARACTERISTICS ..................................................................... 6 TERMINOLOGY ............................................................................................................... 8 SIGNAL TIMING REQUIREMENTS ...................................................................... 9 SYSTEM CLOCK TIMING ................................................................................................ 9 AUDIO INTERFACE TIMING MASTER MODE ............................................................ 9 AUDIO INTERFACE TIMING SLAVE MODE .............................................................. 10 CONTROL INTERFACE TIMING 3-WIRE MODE ....................................................... 11 CONTROL INTERFACE TIMING 2-WIRE MODE ....................................................... 12 DEVICE DESCRIPTION ...................................................................................... 13 INTRODUCTION ............................................................................................................ 13 INPUT SIGNAL PATH .................................................................................................... 14 ANALOGUE TO DIGITAL CONVERTER (ADC) ............................................................ 19 INPUT LIMITER / AUTOMATIC LEVEL CONTROL (ALC) ............................................ 23 OUTPUT SIGNAL PATH ................................................................................................ 35 ANALOGUE OUTPUTS ................................................................................................. 42 OUTPUT SWITCH ......................................................................................................... 47 DIGITAL AUDIO INTERFACES ..................................................................................... 49 AUDIO SAMPLE RATES ................................................................................................ 54 MASTER CLOCK AND PHASE LOCKED LOOP (PLL) ................................................. 55 GENERAL PURPOSE INPUT/OUTPUT ........................................................................ 57 CONTROL INTERFACE ................................................................................................. 57 RESETTING THE CHIP ................................................................................................. 59 POWER SUPPLIES ....................................................................................................... 59 POWER MANAGEMENT ............................................................................................... 63 REGISTER MAP .................................................................................................. 65 REGISTER BITS BY ADDRESS .................................................................................... 66 DIGITAL FILTER CHARACTERISTICS .............................................................. 78 TERMINOLOGY ............................................................................................................. 78 DAC FILTER RESPONSES ........................................................................................... 79 ADC FILTER RESPONSES ........................................................................................... 79 DE-EMPHASIS FILTER RESPONSES .......................................................................... 80 HIGH-PASS FILTER ...................................................................................................... 81 5-BAND EQUALISER ..................................................................................................... 82 APPLICATIONS INFORMATION ........................................................................ 86 RECOMMENDED EXTERNAL COMPONENTS ............................................................ 86 PACKAGE DIAGRAM ......................................................................................... 87 IMPORTANT NOTICE ......................................................................................... 88 REVISION HISTORY ........................................................................................... 89 2 Rev 4.7