WM8988 w Stereo CODEC for Portable Audio Applications DESCRIPTION FEATURES DAC SNR 100dB (A weighted), THD 90dB at 48kHz, 3.3V The WM8988 is a low power, high quality stereo CODEC ADC SNR 93dB (A weighted), THD -81dB at 48kHz, 3.3V designed for portable digital audio applications. Programmable ALC / Noise Gate The device integrates complete interfaces to 2 stereo 2x On-chip Headphone Drivers headphone or line out ports. External component - >40mW output power on 16 / 3.3V requirements are drastically reduced as no separate - THD 80dB at 20mW, SNR 90dB with 16 load headphone amplifiers are required. Advanced on-chip digital Digital Graphic Equaliser signal processing performs graphic equaliser, 3-D sound Low Power enhancement and automatic level control for the - 7mW stereo playback (1.8V / 1.5V supplies) microphone or line input. - 14mW record and playback (1.8V / 1.5V supplies) Low Supply Voltages The WM8988 can operate as a master or a slave, with - Analogue 1.8V to 3.6V various master clock frequencies including 12 or 24MHz for - Digital core: 1.42V to 3.6V USB devices, or standard 256fs rates like 12.288MHz and - Digital I/O: 1.8V to 3.6V 24.576MHz. Different audio sample rates such as 96kHz, 256fs / 384fs or USB master clock rates: 12MHz, 24MHz 48kHz, 44.1kHz are generated directly from the master Audio sample rates: 8, 11.025, 16, 22.05, 24, 32, 44.1, 48, clock without the need for an external PLL. 88.2, 96kHz generated internally from master clock The WM8988 operates at supply voltages down to 1.8V, 4x4mm COL package although the digital core can operate at voltages down to 1.42V to save power, and the maximum for all supplies is APPLICATIONS 3.6 Volts. Different sections of the chip can also be powered Portable Multimedia players down under software control. Multimedia handsets The WM8988 is supplied in a very small and thin 4x4mm Handheld gaming COL package, ideal for use in hand-held and portable systems. BLOCK DIAGRAM DGND DCVDD DBVDD HPGND HPVDD LMIXSEL M U X W LEFT LI2LO DC MEASUREMENT WM8988 MIXER LD2LO LINPUT1 M PGA LOUT1 LINPUT2 U + MIC (headphone / line output RD2LO X BOOST RI2LO LOUT1VOL ADC DAC DIGITAL DIGITAL LINSEL FILTERS FILTERS DIFF. INPUT ANALOGUE GRAPHIC VOLUME HPCOM L1-R1 OR MONO MIX EQUALISER L2-R2 DIGITAL RINSEL BASS MONO MIX BOOST ADC DAC RIGHT M PGA LI2RO MIXER LD2RO U + MIC RINPUT2 X BOOST ROUT1 RINPUT1 (headphone / line output RD2RO ROUT1VOL DC MEASUREMENT RI2RO LOUT2 M (headphone / line output U LOUT2VOL X RMIXSEL LCOM AUDIO CLOCK CONTROL ROUT2 INTERFACE CIRCUITRY INTERFACE 50K 50K (headphone / line output ROUT2VOL Production Data, October 2013, Rev 4.1 WOLFSON MICROELECTRONICS plc Copyright 2013 Wolfson Microelectronics plc AGND VMID AVDD VREF BCLK ADCDAT LRC DACDAT MCLK MODE SCLK SDIN CSBWM8988 Production Data TABLE OF CONTENTS DESCRIPTION ....................................................................................................... 1 FEATURES ............................................................................................................ 1 APPLICATIONS ..................................................................................................... 1 BLOCK DIAGRAM ................................................................................................ 1 TABLE OF CONTENTS ......................................................................................... 2 PIN CONFIGURATION AND DEVICE MARKING ................................................. 3 ORDERING INFORMATION .................................................................................. 3 PIN DESCRIPTION ................................................................................................ 4 ABSOLUTE MAXIMUM RATINGS ........................................................................ 5 RECOMMENDED OPERATION CONDITIONS ..................................................... 5 ELECTRICAL CHARACTERISTICS ..................................................................... 6 POWER CONSUMPTION .................................................................................... 10 SIGNAL TIMING REQUIREMENTS .................................................................... 11 SYSTEM CLOCK TIMING .............................................................................................. 11 AUDIO INTERFACE TIMING MASTER MODE .......................................................... 11 AUDIO INTERFACE TIMING SLAVE MODE .............................................................. 12 INTERNAL POWER ON RESET CIRCUIT .......................................................... 15 DEVICE DESCRIPTION ...................................................................................... 16 INTRODUCTION ............................................................................................................ 16 INPUT SIGNAL PATH .................................................................................................... 16 AUTOMATIC LEVEL CONTROL (ALC) ......................................................................... 23 OUTPUT SIGNAL PATH ................................................................................................ 27 ANALOGUE OUTPUTS ................................................................................................. 32 ENABLING THE OUTPUTS ........................................................................................... 34 THERMAL SHUTDOWN ................................................................................................ 34 DIGITAL AUDIO INTERFACE ........................................................................................ 35 AUDIO INTERFACE CONTROL .................................................................................... 38 CLOCKING AND SAMPLE RATES ................................................................................ 40 CONTROL INTERFACE................................................................................................. 42 POWER SUPPLIES ....................................................................................................... 43 POWER MANAGEMENT ............................................................................................... 43 REGISTER MAP .................................................................................................. 47 DIGITAL FILTER CHARACTERISTICS .............................................................. 48 TERMINOLOGY ............................................................................................................. 48 DAC FILTER RESPONSES ........................................................................................... 49 ADC FILTER RESPONSES ........................................................................................... 50 DE-EMPHASIS FILTER RESPONSES .......................................................................... 51 HIGHPASS FILTER ....................................................................................................... 52 APPLICATIONS INFORMATION ........................................................................ 53 RECOMMENDED EXTERNAL COMPONENTS ............................................................ 53 LINE INPUT CONFIGURATION ..................................................................................... 54 HEADPHONE OUTPUT CONFIGURATION .................................................................. 54 LINE OUTPUT CONFIGURATION ................................................................................. 54 MINIMISING POP NOISE AT THE ANALOGUE OUTPUTS.......................................... 55 POWER MANAGEMENT EXAMPLES ........................................................................... 55 PACKAGE DIMENSIONS .................................................................................... 56 IMPORTANT NOTICE ......................................................................................... 57 ADDRESS ...................................................................................................................... 57 REVISION HISTORY ........................................................................................... 58 PD, Rev 4.1, October 2013 w 2