CMX649E3 CML Microcircuits

CMX649 CML Microcircuits COMMUNICATION SEMICONDUCTORS ADM Codec D/649/6 February 2013 Features Internal and External Sample Clocking Multiple Codec Modes, 16 to 128 kbps Programmable Filters - Full duplex ADM and CVSD - Encoder mic input ADC anti-alias - Full duplex PCM: -law, A-law, Linear - Decoder audio out DAC anti-imaging - Configurable ADM time constants Low Noise Differential Mic Input Amp - Dual channel transcoder/decoder mode Programmable Analog Interface Gain High Performance Digital Architecture - Microphone in Low Power: 2.4mA at 3.0V typ. - Decoder audio out 2.7V - 5.5V Supply - Sidetone path Data Clock Recovery Programmable Voice Activity Detector (VAD) - Adjust threshold level and attack/decay Applications time Low Cost Digital Cordless Headset - Use to powersave on low signal level Personal Area Network (PAN) Voice Link - Silence/blank low level signals Digital Cordless Telephone Programmable Digital Scrambler Wireless Digital PBX Flexible Interfaces Full Duplex Digital Radio Systems - 8-bit and 16-bit burst data with sync Time Division Duplex (TDD) Systems strobe Portable Digital Voice Communicator - 1 bit serial data with clock Digital Voice Delay - Host serial control/data interface Data & Data & XTAL/ XTAL Clock ENCODER Sample Sample Clock Osc Gen Clocks Clocks PCM Tx VAD Transcode Buffer Scramble TX data Analog ADM Input serial Serial MIC control Transcoded Data Control I/O AMP & data sidetone & Status ADM Analog Data & Clock + Rx VAD Transcode Buffer Descramble RX data Output Recovery PCM DECODER 1. Brief Description The CMX649 Adaptive Delta Modulation (ADM) Voice Codec provides full duplex ADM, companded (/A- law) PCM and linear PCM codec and transcoder functions for cost effecive, low power, wireless voice applications. Selectable modes and algorithms support many requirements. Robust ADM coding (e.g. CVSD) reduces host protocol and software burdens, eliminating forward error correction, framing protocols and algorithm processing. Dual transcode/decode mode supports multichannel applications. Integrated filter responses adjust independently of 16kbps to 128kbps codec data rates. Codec sample clocks are externally applied or internally generated. High performance analog interfaces and sidetone include digital gain controls. Encoder and decoder voice activity detectors support powersaving. The CMX649 ADM Voice Codec supports 2.7V to 5.5V operation and is available in 20-pin SOIC (D3) and TSSOP packages (E3) packages. 2013 CML Microsystems Plc ADM Codec CMX649 CONTENTS Section Page 1. Brief Description ..................................................................................... 1 2. Block Diagram ......................................................................................... 4 3. Signal List ................................................................................................ 5 4. External Components ............................................................................. 6 5. General Description ................................................................................ 7 5.1 Block Descriptions ..................................................................... 7 5.1.1 ADM Coding Engine ...................................................... 7 5.1.2 PCM Encoding and Decoding ...................................... 8 5.1.3 Transcoding with the Encoder and Decoder ............. 9 5.1.4 Non-Linear Instantaneous Companding................... 10 5.1.5 Digitally Controlled Amplifiers ................................... 10 5.1.6 Microphone Amplifier ................................................. 10 5.1.7 Programmable Anti-alias/image SC Filters ............... 11 5.1.8 Data Clock Recovery .................................................. 12 5.1.9 Data Scrambler/De-scrambler .................................... 12 5.1.10 Voice Activity Detector (VAD) .................................... 13 5.2 C-BUS Description ................................................................... 14 5.2.1 Write Only Register Description ................................ 17 5.2.1.1 GENERAL RESET ........................................... 17 5.2.1.2 AAF/AIF BANDWIDTH .................................... 17 5.2.1.3 VOLUME/SIDETONE LEVEL .......................... 18 5.2.1.4 AUDIO INPUT LEVEL CONTROL .................. 19 5.2.1.5 POWER CONTROL 1 ...................................... 19 5.2.1.6 POWER CONTROL 2 ...................................... 20 5.2.1.7 CODEC MODE CONTROL ............................. 21 5.2.1.8 SCRAMBLER CONTROL ............................... 21 5.2.1.9 CLK DIVIDER CONTROL ............................... 22 5.2.1.10 CLK SOURCE CONTROL .............................. 24 5.2.1.11 CODEC INTERRUPT CONTROL ................... 25 5.2.1.12 DECODER MODE AND SETUP...................... 26 5.2.1.13 DECODE ADM CONTROL .............................. 27 5.2.1.14 DECODE VAD THRESHOLD .......................... 29 5.2.1.15 DECODE OFFSET LEVEL .............................. 29 5.2.1.16 DECODE LINEAR PCM INPUT....................... 29 5.2.1.17 DECODE ADM INPUT ..................................... 29 5.2.1.18 ENCODER MODE AND SETUP...................... 30 5.2.1.19 ENCODE ADM CONTROL .............................. 32 5.2.1.20 ENCODE VAD THRESHOLD .......................... 33 5.2.1.21 ENCODE OFFSET LEVEL .............................. 33 5.2.1.22 ENCODE DAC INPUT ..................................... 34 5.2.1.23 ENCODE ADM INPUT TEST .......................... 34 5.2.2 Read Only Register Description ................................ 35 5.2.2.1 PROCESSOR STATUS READ ........................ 35 5.2.2.2 DECODE VAD LEVEL OUTPUT READ .......... 35 5.2.2.3 DECODE OFFSET LEVEL OUTPUT READ ... 35 5.2.2.4 DECODE LINEAR PCM OUTPUT READ ....... 35 5.2.2.5 DECODE ADM OUTPUT READ ...................... 36 2013 CML Microsystems Plc 2 D/649/6